19962017

Research output per year

If you made any changes in Pure these will be visible here soon.

Research Output

2017

A Benes̆ Based NoC Switching Architecture for Mixed Criticality Embedded Systems

Kerrison, S., May, D. & Eder, K., Jan 2017, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2016): Proceedings of a meeting held 21-23 September 2016, Lyon, France. Institute of Electrical and Electronics Engineers (IEEE), p. 125-132 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
3 Citations (Scopus)
287 Downloads (Pure)
2015

Synchronising groups of threads with dedicated hardware logic

May, D., 24 Feb 2015, Patent No. US 8,966,488

Research output: Patent

2014
2012

Emulating a large memory sequential machine with a collection of small memory ones

Hanlon, J., Hollis, S. J. & May, D., 3 Oct 2012, In : arXiv. 1210.1158, 1210.1158.

Research output: Contribution to journalArticle (Academic Journal)

59 Downloads (Pure)

Interface processor

May, D., 10 Jul 2012, IPC No. G06F 9/00 9/30, Patent No. US8219789

Research output: Patent

Processor communication tokens

May, D., 17 Jun 2012, IPC No. G06F 15/16, Patent No. US8224884

Research output: Patent

Processor instruction set for controlling threads to respond to events

May, D., 22 May 2012, IPC No. G06F 9/40, Patent No. US8185722

Research output: Patent

Scalable data abstractions for distributed parallel computations

Hanlon, J., Hollis, S. J. & May, D., 3 Oct 2012, In : arXiv. 1210.1157.

Research output: Contribution to journalArticle (Academic Journal)

File
155 Downloads (Pure)

The XMOS Architecture and XS1 Chips

May, D., 2012, (Accepted/In press) In : IEEE Micro. 32, 6, 11 p.

Research output: Contribution to journalArticle (Academic Journal)

8 Citations (Scopus)

Token protocol

May, D., 20 Mar 2012, IPC No. H04L 12/403, Patent No. US8139601

Research output: Patent

2011

A Design-for-Verification Framework for a Configurable Performance-Critical Communication Interface

Abu Kharmeh, S., Eder, KI. & May, MD., Sep 2011, Formal Modeling and Analysis of Timed Systems: 9th International Conference, FORMATS 2011, Aalborg, Denmark, September 21-23, 2011, Proceedings. Palgrave Macmillan, p. 335 - 351

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

5 Citations (Scopus)

Managing Complexity Through Abstraction: A refinement-based approach to formalize Instruction Set Architectures

Yuan, F., Wright, S., Eder, K. I. & May, D., Oct 2011, 13th International Conference on Formal Engineering Methods (ICFEM): Lecture Notes in Computer Science. Springer, Vol. 6991. p. 585-600 (Lecture Notes in Computer Science).

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)

Message routing scheme

May, D., 14 Jun 2011, IPC No. G06F 15/00, Patent No. US7962717

Research output: Patent

Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected

May, D., 7 Jun 2011, IPC No. G06F 9/30 9/40 13/00 13/28 3/00, Patent No. US7958333

Research output: Patent

2010

Compact instruction set encoding

May, D., 9 Mar 2010, IPC No. G06F 9/00, Patent No. US7676653

Research output: Patent

Formal Analysis of a Programmable Performance-Critical Processor Communication Interface

Abu Kharmeh, S., Eder, K. & May, D., 2010, Proceedings of the 10th International Workshop on Automated Verification of Critical Systems (AVoCS 2010). tbc

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

2009

Communicating process architecture for multicores

May, D., 23 Oct 2009, In : Concurrency and Computation: Practice and Experience. 22, 8, p. 935-948 14 p.

Research output: Contribution to journalArticle (Academic Journal)

Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor

May, D., Hedinger, P. & Dixon, A., 3 Nov 2009, IPC No. G06F 13/14, Patent No. US7613909

Research output: Patent

Scheduling thread upon ready signal set when port transfers data on trigger time activation

May, D., Hedinger, P. & Dixon, A., 10 Nov 2009, IPC No. G06F 13/00, Patent No. US7617386

Research output: Patent

The XMOS XS1 Architecture

May, D., 2009, Bristol, UK: XMOS Semiconductor Ltd. 261 p.

Research output: Book/ReportAuthored book

2007

Communicating process architecture for multicores (CPA 2007)

May, MD., 2007, Communicating Process Architectures, CPA 2007, University of Surrey, Guildford, 8-11 July. McEwan, A. A., Ifill, W. & Welch, P. H. (eds.). IOS Press, p. 21 - 32 12 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

2006

A Language and Processor for Unifying System-on-Chip Design

Watt, D. & May, MD., 2006, Department of Computer Science, University of Bristol.

Research output: Working paperWorking paper and Preprints

CSPIC - a Low-power Microcontroller

May, D., 2006, Department of Computer Science, University of Bristol.

Research output: Working paperWorking paper and Preprints

2002

Caches with compositional performance

Irwin, J. P. J., Page, D., May, D. & Muller, H. L., 2002, Embedded Processor Design Challenges. Springer Berlin Heidelberg, Vol. 2268. p. 242-259

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

6 Citations (Scopus)

Predictable instruction caching for media processors

Irwin, J. P. J., Page, D., May, D. & Muller, H. L., 2002, Application-specific Systems, Architectures and Processors - ASAP 2002. Institute of Electrical and Electronics Engineers (IEEE), p. 141 - 150 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

7 Citations (Scopus)
2001

Copying, Moving and Borrowing semantics

May, D. & Muller, HL., Sep 2001, Unknown. Chalmers, A., Mirmehdi, M. & Muller, H. (eds.). IOS Press, p. 51 - 62 11 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Non-deterministic Processors

May, D., Muller, H. & Smart, N., Jul 2001, Information, Security and Privacy - ACISP 2001. Springer Berlin Heidelberg, Vol. 2119. p. 115 - 129 15 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Picochip instruction set proposal

May, D., 2001, University of Bristol.

Research output: Working paperWorking paper and Preprints

Random Register Renaming to Foil DPA

May, D., Muller, H. & Smart, N., May 2001, Cryptographic Hardware and Embedded Systems - CHES 2001. Springer Berlin Heidelberg, Vol. 2162. p. 28 - 38 11 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

55 Citations (Scopus)

The 'Uniform Heterogeneous Multi-threaded' Processor Architecture

Towner, DW. & May, MD., Sep 2001, Communicating Process Architectures 2001. IOS Press, p. 103 - 116 13 p. (Concurrent Systems Engineering Series; vol. 59).

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

2000

Cache Memory

May, D. & Muller, H., 2000, Patent No. WO045269

Research output: Patent

Cache Memory

May, D. & Henk, M., 2000

Research output: Patent

Cache Memory

Muller, HL. & May, MD., 2000, Patent No. WO045269

Research output: Patent

Effective caching for multithreaded processors

May, D., Irwin, J., Muller, H. L. & Page, D., 2000, Communicating Process Architectures - CPA 2000. IOS Press, p. 145-154 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Hardware Migratable Channels

May, D., Henk, M. & Shondip, S., 2000, Department of Computer Science, University of Bristol.

Research output: Working paperWorking paper and Preprints

Hardware Migratable Channels

May, D., Muller, H. & Sen, S., 2000, Euro-Par 2000 (ACM/IFIP/IEEE) Parallel Processing. Springer Berlin Heidelberg, p. 545 - 549 4 p. (Lecture Notes in Computer Science; vol. 1900).

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Hardware Migratable Channels

May, D., Henk, M. & Shondip, S., 2000, In : Euro-Par 2000 Parallel Processing. p. 545-549

Research output: Contribution to journalArticle (Academic Journal)

Synchronisation in a Multithreaded Processor

Shondip, S., P. H., W., Henk, M., A. W. P., B. & May, D., 2000, In : Communicating Process Architectures 2000. p. 137-144

Research output: Contribution to journalArticle (Academic Journal)

Synchronisation in a Multithreaded Processor

Sen, S., Muller, H. & May, D., 2000, Unknown. IOS Press, p. 137 - 144 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

The Transputer Revisted

May, MD., 2000, Millenial Perspectives in Computer Science. Davies, J., Roscoe, B. & Woodcock, J. (eds.). Palgrave Macmillan, p. 215 - 228

Research output: Chapter in Book/Report/Conference proceedingChapter in a book

1999

A cache system

May, D. & Sturges, A., 1999, Patent No. EP890149

Research output: Patent

Interrupt and control packets for a microcomputer

May, D. & Jones, A., 1999, Patent No. EP959412

Research output: Patent

Microcaches

May, D., Page, D., Irwin, J. & Muller, H. L., 1999, High Performance Computing - HiPC 1999. Springer Berlin Heidelberg, Vol. 1745. p. 21-27

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Microcomputer chips with interconnected address and data paths

May, D. & Jones, A., 1999, Patent No. EP953916

Research output: Patent

Microcomputer with bit packets for interrupts, control and memory access

May, D. & Jones, A., 1999, Patent No. EP953914

Research output: Patent

Microcomputer with interrupt packets

May, D. & Jones, A., 1999, Patent No. EP953913

Research output: Patent

Microcomputer with packet translation for event packets and memory access packets

May, D. & Jones, A., 1999, Patent No. EP953915

Research output: Patent

Packet distribution in a microcomputer

May, D. & Jones, A., 1999, Patent No. EP959411

Research output: Patent