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Personal profile

Research interests

  • Computer Architecture
  • New Architecture

Over the last few months, I have been experimenting with some ideas to align
architecture with modern programming languages and new application areas
such as Robotics and IoT. This was prompted by discussions with students and

An important part of this work has been the design of a fast hardware memory
allocation system, integrated into the processor.

It is described briefly here: The SURE Architecture

A more extensive explanation is: The SURE Architecture - long version


I am a Professor at the University of Bristol's Computer Science department. I worked for 16 years in the microelectronics industry. I am well known for my work on innovative microprocessors including the Inmos transputer. I am the author of over 100 papers and patents and I have given numerous conference presentations. In 1990, I was elected a Fellow of the Royal Society for my contributions to computer architecture and parallel computing. My current research interests are in microprocessor architecture system design and verification; mobile, wearable and pervasive computing. I maintain active relationships with industry and technology investors, and I am on the Technical Advisory Board of several recent microelectronics design companies.


  • Computer Architecture
  • Robotics

Fingerprint Dive into the research topics where David May is active. These topic labels come from the works of this person. Together they form a unique fingerprint.


QuPIC: Quantum Technology Capital: Quantum Photonic Integrated Circuits

Thompson, M. G., O'Brien, J. L., May, D., Cryan, M. J., Marshall, G. D., Kling, L., Murray, W. A., Sahin, D., Barreto, J., Coimbatore Balram, K. & Jiang, P.


Project: Research, Parent

Research Output

Lost in translation: Exposing hidden compiler optimization opportunities

Georgiou, K., Chamski, Z., Amaya Garcia, A., May, D. & Eder, K. I., 7 Aug 2020, In : The Computer Journal. 18 p., bxaa103.

Research output: Contribution to journalArticle (Academic Journal)

  • A Benes̆ Based NoC Switching Architecture for Mixed Criticality Embedded Systems

    Kerrison, S., May, D. & Eder, K., Jan 2017, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2016): Proceedings of a meeting held 21-23 September 2016, Lyon, France. Institute of Electrical and Electronics Engineers (IEEE), p. 125-132 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

    Open Access
  • 3 Citations (Scopus)
    305 Downloads (Pure)