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Research output per year

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Research Output

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Conference Contribution (Conference Proceeding)
2018

Multi-precision convolutional neural networks on heterogeneous hardware

Amiri, S., Hosseinabady, M., McIntosh-Smith, S. & Nunez-Yanez, J., 23 Apr 2018, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018. Institute of Electrical and Electronics Engineers (IEEE), p. 419-424 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
3 Citations (Scopus)
346 Downloads (Pure)

Optimal compression of vibration data with lifting wavelet transform and context-based arithmetic coding

Zhang, Y., Hutchinson, P., Lieven, N. A. J. & Nunez-Yanez, J., Jan 2018, 2017 25th European Signal Processing Conference (EUSIPCO 2017): Proceedings of a meeting held 28 August - 2 September 2017, Kos, Greece. Institute of Electrical and Electronics Engineers (IEEE), p. 1996-2000 5 p. 8081559

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
2 Citations (Scopus)
192 Downloads (Pure)

Pipelined Streaming Computation of Histogram in FPGA OpenCL

Hosseinabady, M. & Nunez-Yanez, J. L., 7 Mar 2018, Parallel Computing is Everywhere. IOS Press, p. 632-641 10 p. (Advances in Parallel Computing; vol. 32).

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
1 Citation (Scopus)
169 Downloads (Pure)

Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip

Nunez-Yanez, J., Hosseinabady, M., Rodríguez, A., Asenjo, R., Navarro, A., Gran-Tejero, R. & Suárez-Gracia, D., 7 Mar 2018, Parallel Computing is Everywhere. IOS Press, p. 677-686 10 p. (Advances in Parallel Computing; vol. 32).

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
52 Downloads (Pure)

Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources

Chen, Q., Mishra, V., Nunez-Yanez, J. & Zervas, G., 2 Feb 2018, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. Institute of Electrical and Electronics Engineers (IEEE), Vol. 2018-January. p. 1-6 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)
2017

A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis

Hosseinabady, M. & Nunez-Yanez, J. L., 5 Oct 2017, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers (IEEE), 4 p. 8056758

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
2 Citations (Scopus)
218 Downloads (Pure)

CPCIe: A Compression-enabled PCIe Core for Energy and Performance Optimization

Bin Zainol, M. A. & Nunez-Yanez, J. L., Feb 2017, 2016 IEEE Nordic Circuits and Systems Conference (NORCAS 2016): Proceedings of a meeting held 1-2 December 2016, Copenhagen, Denmark. Institute of Electrical and Electronics Engineers (IEEE), p. 127-132 6 p. 7792892

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
366 Downloads (Pure)

SiP-enabled FPGA Network Interface for Programmable Access to Disaggregated Data Centre Resources

Chen, Q., Mishra, V., De Dobbelaere, P., Enrico, M., Parsons, N., Nunez-Yanez, J. & Zervas, G., 9 Aug 2017, Asia Communications and Photonics Conference, ACPC 2017. Optical Society of America (OSA), Vol. Part F83-ACPC 2017. Su2A.78

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

2016

Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application

Nunez-Yanez, J. L., 13 Mar 2016, Applied Reconfigurable Computing: 12th International Symposium, ARC 2016 Mangaratiba, RJ, Brazil, March 22–24, 2016 Proceedings. Bonato, V., Bouganis, C. & Gorgon, M. (eds.). Springer Verlag, p. 41-53 13 p. (Lecture Notes in Computer Science; vol. 9625).

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
1 Citation (Scopus)
283 Downloads (Pure)

Energy efficient video fusion with heterogeneous CPU-FPGA devices

Sun, P., Achim, A., Hasler, I., Hill, P. & Nunez-Yanez, J., Jun 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE 2016): Proceedings of a meeting held 14-18 March 2016, Dresden, Germany. Institute of Electrical and Electronics Engineers (IEEE), p. 1399-1404 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
1 Citation (Scopus)
207 Downloads (Pure)

Energy proportional computing with OpenCL on a FPGA-based overlay architecture

Sani, A. H. & Nunez-Yanez, J. L., 22 Dec 2016, Proceedings of the 2nd IEEE NORCAS Conference (NORCAS 2016). Institute of Electrical and Electronics Engineers (IEEE), 6 p. 7792905

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
1 Citation (Scopus)
235 Downloads (Pure)

Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture

Nikov, K., Nunez-Yanez, J. L. & Horsnell, M., Mar 2016, 2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing (EUC 2015): Proceedings of a meeting held 21-23 October 2015, Porto, Portugal. Institute of Electrical and Electronics Engineers (IEEE), p. 205-210 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
8 Citations (Scopus)
320 Downloads (Pure)
2015

Energy Optimization of FPGA-Based Stream-Oriented Computing with Power Gating

Hosseinabady, M. & Nunez-Yanez, J., Dec 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL 2015): Proceedings of a meeting held 2-4 September 2015, London, United Kingdom. Institute of Electrical and Electronics Engineers (IEEE), 6 p. 7293946

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
5 Citations (Scopus)
313 Downloads (Pure)

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices

Hosseinabady, M. & Nunez-Yanez, J. L., 7 Oct 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL 2015): Proceedings of a meeting held 2-4 September 2015, London, United Kingdom. Institute of Electrical and Electronics Engineers (IEEE), 6 p. 7294016. (International Conference on Field-programmable Logic and Applications Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
6 Citations (Scopus)
565 Downloads (Pure)

Power modelling and capping for heterogeneous ARM/FPGA SoCs

Wu, Y., Nunez-Yanez, J., Woods, R. & Nikolopoulos, D. S., 8 Apr 2015, Proceedings of the 2014 International Conference on Field-Programmable Technology, FPT 2014. Institute of Electrical and Electronics Engineers (IEEE), p. 231-234 4 p. 7082782

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

5 Citations (Scopus)

Workload distribution and balancing in FPGAs and CPUs with OpenCL and TBB

Asenjo, R., Navarro, A., Rodriguez, A. & Nunez-Yanez, J., 1 Sep 2015, Parallel Computing: On the Road to Exascale. Joubert, G. R., Leather, H., Parsons, M., Peters, F. & Sawyer, M. (eds.). IOS Press, p. 543-551 9 p. (Advances in Parallel Computing; vol. 27).

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
1 Citation (Scopus)
164 Downloads (Pure)
2014

Accurate power control and monitoring in ZYNQ boards

Beldachi, A. F. & Nunez-Yanez, J. L., 1 Jan 2014, Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers (IEEE), 6927415

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

14 Citations (Scopus)

Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling.

Nunez-Yanez, J. L., 3 Dec 2014, ACM SIGARCH Computer Architecture News: HEART '14. DeGroot, D. (ed.). 4 ed. Association for Computing Machinery (ACM), Vol. 42. p. 87-92 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
121 Downloads (Pure)

Neuron dynamics of two-compartment traub model for hardware-based emulation

Moctezuma, J. C., Nunez-Yanez, J. L. & McGeehan, J. P., 1 Jan 2014, NCTA 2014 - Proceedings of the International Conference on Neural Computation Theory and Applications. INSTICC Press, p. 85-93 9 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Run-time power and performance scaling with CPU-FPGA hybrids

Nunez-Yanez, J. & Farhadi Beldachi, A. F., 17 Jul 2014, 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS). Institute of Electrical and Electronics Engineers (IEEE), p. 55-60 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
6 Citations (Scopus)
271 Downloads (Pure)

Run-time power gating in hybrid ARM-FPGA devices

Hosseinabady, M. & Nunez-Yanez, J. L., 1 Jan 2014, Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers (IEEE), 6927503

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

18 Citations (Scopus)
2013

Approximate alpha-stable Markov Random Fields for video super-resolution

Chen, J., Nunez-Yanez, J. & Achim, A., Jan 2013, 2012 Proceedings of the 20th European Signal Processing Conference (EUSIPCO 2012) . Institute of Electrical and Electronics Engineers (IEEE), p. 2738-2742 5 p. (Proceedings of the European Signal Processing Conference (EUSIPCO)).

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)

Energy proportional computing in commercial FPGAs with adaptive voltage scaling

Nunez-Yanez, J., 24 Oct 2013, 10th FPGAworld Conference - Academic Proceedings 2013, FPGAworld 2013. 6

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

7 Citations (Scopus)

Numerically efficient and biophysically accurate neuroprocessing platform

Moctezuma, J. C., McGeehan, J. P. & Nunez-Yanez, J. L., 1 Jan 2013, 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013. IEEE Computer Society, 6732313

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

2 Citations (Scopus)

Video super-resolution using low rank matrix completion

Chen, J., Nunez-Yanez, J. & Achim, A., 1 Dec 2013, 2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings. p. 1376-1380 5 p. 6738283

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

4 Citations (Scopus)
2009

A biophysically accurate floating point somatic neuroprocessor

Zhang, Y., Nunez-Yanez, JL., McGeehan, JP., Regan, EM. & Kelly, S., Aug 2009, International Conference on Field Programmable Logic and Applications, 2009 (FPL 2009), Prague. Institute of Electrical and Electronics Engineers (IEEE), p. 26 - 31 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
10 Citations (Scopus)
631 Downloads (Pure)

A toolset for the analysis and optimization of motion estimation algorithms and processors

Spiteri, T., Vafiadis, G. & Nunez-Yanez, JL., Aug 2009, International Conference on Field Programmable Logic and Applications, 2009 (FPL 2009), Prague. Institute of Electrical and Electronics Engineers (IEEE), p. 423 - 428 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
3 Citations (Scopus)
488 Downloads (Pure)

Run-time resource management in fault-tolerant network on reconfigurable chips

Hosseinabady, M. & Nunez-Yanez, JL., Aug 2009, International Conference on Field Programmable Logic and Applications, 2009 (FPL 2009), Prague. Institute of Electrical and Electronics Engineers (IEEE), p. 574 - 577 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
5 Citations (Scopus)
411 Downloads (Pure)
2008

A configurable and programmable motion estimation processor for the H.264 video codec

Nunez-Yanez, JL., Eddie, H. & Chouliaras, V., 8 Sep 2008, International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany. p. 149 - 154 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

17 Citations (Scopus)

Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor

Zaidi, SIH., Nabina, A., Canagarajah, CN. & Nunez-Yanez, JL., Sep 2008, International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg. Institute of Electrical and Electronics Engineers (IEEE), p. 547 - 550 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
8 Citations (Scopus)
475 Downloads (Pure)

Fault-tolerant dynamically reconfigurable NoC-based SoC

Hosseinabady, M. & Nunez-Yanez, JL., 2 Jul 2008, International Conference on Application-Specific Systems, Architectures and Processors (ASAP2008), Leuven, Belgium. Institute of Electrical and Electronics Engineers (IEEE), p. 31 - 36 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

12 Citations (Scopus)

Lossless compression for space imagery in a dynamically reconfigurable architecture

Chen, X., Canagarajah, CN., Vitulli, R. & Nunez-Yanez, JL., 26 Mar 2008, 4th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications (ARC 2008), London, UK. Springer, p. 336 - 341 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

4 Citations (Scopus)

Power/area analysis of a FPGA-based open-source processor using partial dynamic reconfiguration

Zaidi, SIH., Nabina, A., Canagarajah, CN. & Nunez-Yanez, JL., Sep 2008, EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008 (DSD '08), Parma. Institute of Electrical and Electronics Engineers (IEEE), p. 592 - 598 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
3 Citations (Scopus)
470 Downloads (Pure)

Statistical lossless compression of space imagery and general data in a reconfigurable architecture

Nunez-Yanez, JL., Chen, X., Canagarajah, CN. & Vitulli, R., Jun 2008, NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2008), Noordwijk, Netherlands. Institute of Electrical and Electronics Engineers (IEEE), p. 172 - 177 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
2 Citations (Scopus)
295 Downloads (Pure)
2007

Dynamic voltage scaling in a FPGA-based system-on-chip

Nunez-Yanez, JL., Chouliaras, VA. & Gaisler, J., 27 Aug 2007, 2007 International Conference on Field Programmable Logic and Applications, (FPL 2007), Amsterdam, Netherlands. Institute of Electrical and Electronics Engineers (IEEE), p. 459 - 462 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

7 Citations (Scopus)

Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding

Chen, X., Canagarajah, CN., Nunez-Yanez, JL. & Vitulli, R., Sep 2007, IEEE International SOC Conference, Hsin Chu, Taiwan. Institute of Electrical and Electronics Engineers (IEEE), p. 251 - 254

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Open Access
File
5 Citations (Scopus)
248 Downloads (Pure)
2006

Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators

Koutsomyti, K., Chouliaras, V., Parr, SR., Nunez-Yanez, JL. & Datta, S., 7 Jan 2006, International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA, 7-11 January. Institute of Electrical and Electronics Engineers (IEEE), p. 279 - 280 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

A novel processor architecture for real-time control

Xiaofeng, W., Chouliaras, V. & Nunez-Yanez, JL., 6 Oct 2006, 11th Asia-Pacific Conference on Advances in Computer Systems Architecture (ACSAC 2006), (Lecture Notes in Computer Science Vol.4186), Shanghai, China. Springer, Vol. 4186. p. 270 - 280 11 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)

Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H.264 advanced video codec

Nunez-Yanez, JL., Chouliaras, VA. & Alfonso, D., 2006, 2006 Digest of Technical Papers International Conference on Consumer Electronics. Institute of Electrical and Electronics Engineers (IEEE), p. 95-96 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

3 Citations (Scopus)
2005

A system-on-chip vector multiprocessor for transmission line modelling acceleration

Chouliaras, VA., Flint, JA., Yibin, L. & Nunez-Yanez, JL., 2 Nov 2005, IEEE Workshop on Signal Processing Systems-Design and Implementation (IEEE Cat. No.05TH8830C), Greece. Institute of Electrical and Electronics Engineers (IEEE), Vol. 1. p. 568 - 572 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)

A thread and data-parallel MPEG-4 video encoder for a system-on-chip multiprocessor

Jacobs, TR., Chouliaras, VA. & Nunez-Yanez, JL., 23 Jul 2005, 16th International Conference on Application-Specific Systems, Architecture and Processors, Greece. Institute of Electrical and Electronics Engineers (IEEE), Vol. 1. p. 405 - 410 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)

Configurable multiprocessors for high-performance MPEG-4 video coding

Chouliaras, VA., Jacobs, TR., Kumaraswamy, A. K. & Nunez-Yanez, JL., 11 May 2005, IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States. IEEE Computer Society, p. 272 - 273 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Configurable scalar and vector coprocessors for accelerating the G.723.1and G.729A speech coders

Parr, SR., Koutsomyti, K., Chouliaras, VA., Nunez-Yanez, JL. & Mulvaney, DJ., 2005, IASTED International Conference on Signal and Image Processing.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Design and implementation of a high-performance and silicon efficient arithmetic coding accelerator for the H.264 advanced video codec

Nunez-Yanez, JL. & Chouliaras, VA., 23 Jul 2005, 16th International Conference on Application-Specific Systems, Architecture and Processors, Greece. Institute of Electrical and Electronics Engineers (IEEE), Vol. 1. p. 411 - 416 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

13 Citations (Scopus)
2004

Arithmetic coding hardware accleration in a SOPC platform for advanced video compression

Nunez-Yanez, JL. & Chouliaras, VA., 2004, International Conference on Reconfigurable Computing and FPGAs, Colima, Mexico.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

A system for fault detection and reconfiguration of hardware based active networks

Bartzoudis, NG., Fragkiadakis, AG., Parish, DJ. & Nunez-Yanez, JL., 12 Jul 2004, 10th IEEE International On-Line Testing Symposium, 2004 (IOLTS 2004), Madeira. Institute of Electrical and Electronics Engineers (IEEE), Vol. 1. p. 207 - 213 7 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Scalar and parametric vector accelerators for the G.729A speech coding standard

Koutsomyti, K., Parr, SR., Chouliaras, VA., Nunez-Yanez, JL., Mulvaney, DJ. & Datta, S., Sep 2004, IEE/ACM SoC Design, Test and Technology Postgraduate Seminar, Lougborough University.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Silicon implementation of a parametric vector datapath for real-time MPEG2 encoding

Chouliaras, VA., Nunez-Yanez, JL. & Agha, S., 23 Aug 2004, Sixth IASTED International Conference on Signal and Image Processing. ACTA Press, Vol. 1. p. 298 - 303 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

7 Citations (Scopus)

The application of thread-level parallelism for reducing the architectural complexity of an MPEG2 encoder

Jacobs, TR., Chouliaras, VA., Mulvaney, DJ. & Nunez-Yanez, JL., Sep 2004, IEE/ACM SoC Design, Test and Technology Postgraduate Seminar, Loughborough University.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

2003

A code compression scheme for improving SoC performance

Nikolova, EG., Mulvaney, DJ., Chouliaras, VA. & Nunez-Yanez, JL., 19 Nov 2003, IEEE 2003 International Symposium on System-on-Chip. Institute of Electrical and Electronics Engineers (IEEE), Vol. 1. p. 35 - 40 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)