DYNAMICALLY RECONFIGURABLE HARDWARE ARCHITECTURES FOR CONTEXT-BASED STATISTICAL COMPRESSION OF VISUAL AND DATA CONTENT

Nunez-Yanez, Jose L (Principal Investigator)

Status	Finished
Effective start/end date	22/02/06 → 22/02/09

5 Article (Academic Journal)

Biologically compatible neural networks with reconfigurable hardware
Moctezuma Eugenio, J. C., McGeehan, J. P. & Nunez-Yanez, J. L., 1 Nov 2015, In: Microprocessors and Microsystems. 39, 8, p. 693-703 11 p.
Research output: Contribution to journal › Article (Academic Journal) › peer-review

Open Access
File
8 Citations (Scopus)

552 Downloads (Pure)
eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip
Farhadi Beldachi, A. F., Hollis, S. J. & Nunez-Yanez, J. L., May 2014, In: IET Computers and Digital Techniques. 8, 3, p. 148-162 15 p.
Research output: Contribution to journal › Article (Academic Journal) › peer-review

Open Access
File
2 Citations (Scopus)

237 Downloads (Pure)
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding
Nunez-Yanez, J., Nabina, A., Hung, E. & Vafiadis, G., 10 Feb 2011, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 3, p. 437-448 12 p.
Research output: Contribution to journal › Article (Academic Journal) › peer-review

File
16 Citations (Scopus)

302 Downloads (Pure)