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LOGIC VERIFICATION, SYNTHESIS AND TEST IN A NEW UNIFIED FRAMEWORK AND LOW POWER TESTABLE DESIGNS

  • Pradhan, Dhiraj K (Principal Investigator)

    Project Details

    StatusFinished
    Effective start/end date20/10/03 → 20/08/07

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    • 2 Article (Academic Journal)

    • C-Testable Bit Parallel Multipliers Over GF(2m)

      Rahaman, H., Mathew, J., Dhiraj, P. & Jamir, A. M., 2008, In: Transactions on Design Automation of Electronic Systems. 13, 1, p. 5-13 -.

      Research output: Contribution to journal › Article (Academic Journal) › peer-review

      7 Citations (Scopus)

    • EBIST: a novel test generator with built-in fault detection capability

      Pradhan, D. & Liu, C., Sept 2005, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24 (9), p. 1457 - 1466 10 p.

      Research output: Contribution to journal › Article (Academic Journal) › peer-review

      10 Citations (Scopus)