PROCESS VARIATION AWARE SYNTHESIS OF NANO-CMOS CIRCUITS

Status	Finished
Effective start/end date	1/10/09 → 1/03/13

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes over GF(2^m)
Poolakkaparambil, M., Mathew, J., Jabir, A. M. & Pradhan, D. K., 1 Aug 2015, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23, 8, p. 1448-1458 11 p., 6876030.
Research output: Contribution to journal › Article (Academic Journal) › peer-review
1 Citation (Scopus)
A hybrid reliability assessment method and its support of sequential logic modelling
Pagliarini, S. N., De Naviner, L. A. B., Naviner, J. F. & Pradhan, D., 2014, Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014. IEEE Computer Society, p. 182-183 2 p. 6873690
Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)
A placement strategy for reducing the effects of multiple faults in digital circuits
Pagliarini, S. N. & Pradhan, D., 2014, Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014. IEEE Computer Society, p. 69-74 6 p. 6873674
Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)
10 Citations (Scopus)

Project Details