PROCESS VARIATION AWARE SYNTHESIS OF NANO-CMOS CIRCUITS

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2015
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes over GF(2^m)
Poolakkaparambil, M., Mathew, J., Jabir, A. M. & Pradhan, D. K., 1 Aug 2015, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23, 8, p. 1448-1458 11 p., 6876030.
Research output: Contribution to journal › Article (Academic Journal) › peer-review
1 Citation (Scopus)
2012
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM
Mohanty, S. P., Singh, J., Kougianos, E. & Pradhan, D. K., Jan 2012, In: Integration, the VLSI Journal archive. 45, 1, p. 33-45 13 p.
Research output: Contribution to journal › Article (Academic Journal) › peer-review
11 Citations (Scopus)
2011
A Routing-Aware ILS Design Technique
Banerjee, S., Mathew, J., Pradhan, D. K., Bhattacharya, B. B. & Mohanty, S. P., Dec 2011, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 12, p. 2335-2338 5 p., -.
Research output: Contribution to journal › Article (Academic Journal) › peer-review

Research output