14-bit 2.2-MS/s sigma-delta ADC's

J Morizio, M Hoke, T Kocak, C et al Geddie

Research output: Contribution to journalArticle (Academic Journal)peer-review

42 Citations (Scopus)
682 Downloads (Pure)

Abstract

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections
Translated title of the contribution14-bit 2.2-MS/s sigma-delta ADC's
Original languageEnglish
Pages (from-to)968 - 976
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume35
Issue number7
DOIs
Publication statusPublished - Jul 2000

Bibliographical note

Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Rose publication type: Journal article

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Keywords

  • cascaded ADC architectures
  • mash ADC architectures
  • switched-capacitor circuits
  • sigma–delta modulators
  • hybrid AD converters
  • analogue circuits

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