14-bit 2.2-MS/s sigma-delta ADC's

J Morizio; M Hoke; T Kocak; C et al Geddie

doi:10.1109/4.848205

14-bit 2.2-MS/s sigma-delta ADC's

J Morizio, M Hoke, T Kocak, C et al Geddie

Department of Electrical & Electronic Engineering

Research output: Contribution to journal › Article (Academic Journal) › peer-review

44 Citations (Scopus)

793 Downloads (Pure)

Abstract

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections

Translated title of the contribution	14-bit 2.2-MS/s sigma-delta ADC's
Original language	English
Pages (from-to)	968 - 976
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	35
Issue number	7
DOIs	https://doi.org/10.1109/4.848205
Publication status	Published - Jul 2000

Bibliographical note

Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Rose publication type: Journal article

Terms of use: Copyright © 2000 IEEE. Reprinted from IEEE Journal of Solid-State Circuits. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org.

By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

Keywords

cascaded ADC architectures
mash ADC architectures
switched-capacitor circuits
sigma–delta modulators
hybrid AD converters
analogue circuits

Access to Document

10.1109/4.848205

Kocak solidstates 2000Accepted author manuscript, 271 KB

http://hdl.handle.net/1983/1038

Cite this

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title = "14-bit 2.2-MS/s sigma-delta ADC's",

abstract = "This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections",

keywords = "cascaded ADC architectures, mash ADC architectures, switched-capacitor circuits, sigma–delta modulators, hybrid AD converters, analogue circuits",

author = "J Morizio and M Hoke and T Kocak and Geddie, {C et al}",

note = "Publisher: Institute of Electrical and Electronics Engineers (IEEE) Rose publication type: Journal article Terms of use: Copyright {\textcopyright} 2000 IEEE. Reprinted from IEEE Journal of Solid-State Circuits. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. ",

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AU - Kocak, T

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N2 - This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections

AB - This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections

KW - cascaded ADC architectures

KW - mash ADC architectures

KW - switched-capacitor circuits

KW - sigma–delta modulators

KW - hybrid AD converters

KW - analogue circuits

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DO - 10.1109/4.848205

M3 - Article (Academic Journal)

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EP - 976

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 7

ER -

14-bit 2.2-MS/s sigma-delta ADC's

Abstract

Bibliographical note

Keywords

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