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This paper presents a 2-transistors-memristors (2T2M) bitcell for content-Addressable memory design suitable for low-power applications. It uses memristors to store data and MOS transistors as access devices. The low power proposed design splits the search lines to search logic 1 and logic 0 separately to reduce the search power consumption. Different word sizes of the proposed bitcells with and without low power structure are simulated, including full parasitics using BPTM, 45nm CMOS technology node to evaluate and compare different performance parameters. The proposed low power design reduces the active power dissipation of about 30% compared to the design with conventional search approach.
|Title of host publication
|Proceedings - 2015 10th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2015
|Institute of Electrical and Electronics Engineers (IEEE)
|Published - 17 Jun 2015
|2015 10th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2015 - Naples, Italy
Duration: 21 Apr 2015 → 23 Apr 2015
|2015 10th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2015
|21/04/15 → 23/04/15
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- 1 Finished
Pradhan, D. K.
24/08/12 → 24/12/15