3-D Integration and the Limits of Silicon Computation

Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use the ECE and ECD to study the limits of performance under different memory distribution, power, thermal and cost constraints for various 2-D and 3-D topologies, in current and future technology nodes.
Original languageUndefined/Unknown
Title of host publicationProc. IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC)
Pages343-348
Number of pages6
DOIs
Publication statusPublished - 1 Oct 2011

Bibliographical note

Invited Presentation, Special Session on Frontier in 3-D Integrated Engineering, Hong Kong

Keywords

  • power semiconductor devices
  • three-dimensional integrated circuits
  • 3D integration
  • effective computational density
  • effective computational efficiency
  • intrinsic computational efficiency
  • power envelope
  • silicon computation
  • through silicon vias
  • vertical links
  • Computational modeling
  • Heating
  • Random access memory

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