3-D Integration and the Limits of Silicon Computation

Dinesh Pamunuwa; Matthew Grange; Roshan Weerasekera; Axel Jantsch

doi:10.1109/VLSISoC.2011.6081605

3-D Integration and the Limits of Silicon Computation

Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Abstract

The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use the ECE and ECD to study the limits of performance under different memory distribution, power, thermal and cost constraints for various 2-D and 3-D topologies, in current and future technology nodes.

Original language	Undefined/Unknown
Title of host publication	Proc. IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC)
Pages	343-348
Number of pages	6
DOIs	https://doi.org/10.1109/VLSISoC.2011.6081605
Publication status	Published - 1 Oct 2011

Bibliographical note

Invited Presentation, Special Session on Frontier in 3-D Integrated Engineering, Hong Kong

Research Groups and Themes

Photonics and Quantum

Keywords

power semiconductor devices
three-dimensional integrated circuits
3D integration
effective computational density
effective computational efficiency
intrinsic computational efficiency
power envelope
silicon computation
through silicon vias
vertical links
Computational modeling
Heating
Random access memory

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10.1109/VLSISoC.2011.6081605

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Cite this

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abstract = "The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use the ECE and ECD to study the limits of performance under different memory distribution, power, thermal and cost constraints for various 2-D and 3-D topologies, in current and future technology nodes.",

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