A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors

P. Maniotis, D. Fitsios, G. T. Kanellos, N. Pleros

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

4 Citations (Scopus)

Abstract

We demonstrate a novel 16GHz physical layer optical cache memory architecture for the 2-way set associative cache mapping scheme. Both memory addresses and optical words are WDM-formatted while physical layer simulations demonstrate successful Read/Write operation.

Original languageEnglish
Title of host publication2014 Optical Fiber Communications Conference and Exhibition, OFC 2014
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISBN (Electronic)9781557529930
ISBN (Print)9781557529930
DOIs
Publication statusPublished - 1 Jan 2014
Event2014 Optical Fiber Communications Conference and Exhibition, OFC 2014 - San Francisco, CA, United States
Duration: 9 Mar 201413 Mar 2014

Conference

Conference2014 Optical Fiber Communications Conference and Exhibition, OFC 2014
CountryUnited States
CitySan Francisco, CA
Period9/03/1413/03/14

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