A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors

P. Maniotis; D. Fitsios; G. T. Kanellos; N. Pleros

doi:10.1109/OFC.2014.6886742

A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors

P. Maniotis
, D. Fitsios
, G. T. Kanellos
, N. Pleros

High Performance Networks Group (HPN)

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

4 Citations (Scopus)

Abstract

We demonstrate a novel 16GHz physical layer optical cache memory architecture for the 2-way set associative cache mapping scheme. Both memory addresses and optical words are WDM-formatted while physical layer simulations demonstrate successful Read/Write operation.

Original language	English
Title of host publication	2014 Optical Fiber Communications Conference and Exhibition, OFC 2014
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
ISBN (Electronic)	9781557529930
ISBN (Print)	9781557529930
DOIs	https://doi.org/10.1109/OFC.2014.6886742
Publication status	Published - 1 Jan 2014
Event	2014 Optical Fiber Communications Conference and Exhibition, OFC 2014 - San Francisco, CA, United States Duration: 9 Mar 2014 → 13 Mar 2014

Conference

Conference	2014 Optical Fiber Communications Conference and Exhibition, OFC 2014
Country/Territory	United States
City	San Francisco, CA
Period	9/03/14 → 13/03/14

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10.1109/OFC.2014.6886742

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@inproceedings{c574ee91f16c4e1b969b6fa28c23533e,

title = "A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors",

abstract = "We demonstrate a novel 16GHz physical layer optical cache memory architecture for the 2-way set associative cache mapping scheme. Both memory addresses and optical words are WDM-formatted while physical layer simulations demonstrate successful Read/Write operation.",

author = "P. Maniotis and D. Fitsios and Kanellos, \{G. T.\} and N. Pleros",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/OFC.2014.6886742",

language = "English",

isbn = "9781557529930",

booktitle = "2014 Optical Fiber Communications Conference and Exhibition, OFC 2014",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "2014 Optical Fiber Communications Conference and Exhibition, OFC 2014 ; Conference date: 09-03-2014 Through 13-03-2014",

}

Maniotis, P, Fitsios, D, Kanellos, GT & Pleros, N 2014, A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors. in 2014 Optical Fiber Communications Conference and Exhibition, OFC 2014., 6886742, Institute of Electrical and Electronics Engineers (IEEE), 2014 Optical Fiber Communications Conference and Exhibition, OFC 2014, San Francisco, CA, United States, 9/03/14. https://doi.org/10.1109/OFC.2014.6886742

A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors. / Maniotis, P.; Fitsios, D.; Kanellos, G. T. et al.
2014 Optical Fiber Communications Conference and Exhibition, OFC 2014. Institute of Electrical and Electronics Engineers (IEEE), 2014. 6886742.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors

AU - Maniotis, P.

AU - Fitsios, D.

AU - Kanellos, G. T.

AU - Pleros, N.

PY - 2014/1/1

Y1 - 2014/1/1

N2 - We demonstrate a novel 16GHz physical layer optical cache memory architecture for the 2-way set associative cache mapping scheme. Both memory addresses and optical words are WDM-formatted while physical layer simulations demonstrate successful Read/Write operation.

AB - We demonstrate a novel 16GHz physical layer optical cache memory architecture for the 2-way set associative cache mapping scheme. Both memory addresses and optical words are WDM-formatted while physical layer simulations demonstrate successful Read/Write operation.

UR - https://www.scopus.com/pages/publications/84907414833

U2 - 10.1109/OFC.2014.6886742

DO - 10.1109/OFC.2014.6886742

M3 - Conference Contribution (Conference Proceeding)

AN - SCOPUS:84907414833

SN - 9781557529930

BT - 2014 Optical Fiber Communications Conference and Exhibition, OFC 2014

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 2014 Optical Fiber Communications Conference and Exhibition, OFC 2014

Y2 - 9 March 2014 through 13 March 2014

ER -

A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessors

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