A 3D bus interconnect for network line cards

J Engel, T Kocak

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

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Abstract

In this paper, we propose a 3D bus architecture as a processor-memory interconnection system to increase the throughput of the memory system currently used on line cards. The 3D bus architecture allows multiple processing elements on a line card to access a shared memory. The main advantage of the proposed architecture is to increase the network processor off-chip memory bandwidth while diminishing the latency otherwise caused by the single bus competition.
Translated title of the contributionA 3D bus interconnect for network line cards
Original languageEnglish
Title of host publication2nd Annual IEEE Northeast Workshop on Circuits and Systems, Montreal, Canada
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages257 - 260
Number of pages4
ISBN (Print)0780383222
DOIs
Publication statusPublished - Jun 2004
Event2nd IEEE Northeast Workshop on Circuits and Systems - Montreal, Canada
Duration: 1 Jun 2004 → …

Conference

Conference2nd IEEE Northeast Workshop on Circuits and Systems
CountryCanada
CityMontreal
Period1/06/04 → …

Bibliographical note

Conference Proceedings/Title of Journal: 2nd Annual IEEE Northeast Workshop on Circuits and Systems
Conference Organiser: IEEE
Rose publication type: Conference contribution

Terms of use: Copyright © 2004 IEEE. Reprinted from IEEE 2nd Annual Northeast Workshop on Circuits and Systems, 2004 (NEWCAS 2004).

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