In this paper, we propose a 3D bus architecture as a processor-memory interconnection system to increase the throughput of the memory system currently used on line cards. The 3D bus architecture allows multiple processing elements on a line card to access a shared memory. The main advantage of the proposed architecture is to increase the network processor off-chip memory bandwidth while diminishing the latency otherwise caused by the single bus competition.
|Translated title of the contribution||A 3D bus interconnect for network line cards|
|Title of host publication||2nd Annual IEEE Northeast Workshop on Circuits and Systems, Montreal, Canada|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Pages||257 - 260|
|Number of pages||4|
|Publication status||Published - Jun 2004|
|Event||2nd IEEE Northeast Workshop on Circuits and Systems - Montreal, Canada|
Duration: 1 Jun 2004 → …
|Conference||2nd IEEE Northeast Workshop on Circuits and Systems|
|Period||1/06/04 → …|
Bibliographical noteConference Proceedings/Title of Journal: 2nd Annual IEEE Northeast Workshop on Circuits and Systems
Conference Organiser: IEEE
Rose publication type: Conference contribution
This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to firstname.lastname@example.org.
By choosing to view this document, you agree to all provisions of the copyright laws protecting it.