A 5.25ps-resolution TDC on FPGA using DSP blocks

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Abstract

With the introduction of its 7-series FPGAs, Xilinx introduced a new iteration of their DSP48 block, the DSP48E1. In our previous paper. we examined the usefulness of its predecessor the DSP48A1, for the generation of high-resolution delays. In this paper, we examine how the DSP48E1 has changed and what this means for the generation of high-resolution delays with this block.
Original languageEnglish
Number of pages5
Publication statusPublished - 30 Apr 2019
EventInternational Conference on Digital Image & Signal Processing - Oxford, United Kingdom
Duration: 29 Apr 201930 Apr 2019

Conference

ConferenceInternational Conference on Digital Image & Signal Processing
CountryUnited Kingdom
CityOxford
Period29/04/1930/04/19

Keywords

  • Time-to-Digital Converters
  • Field Programmable Gate Arrays
  • Xilinx
  • Delay Generation

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