Abstract
With the introduction of its 7-series FPGAs, Xilinx introduced a new iteration of their DSP48 block, the DSP48E1. In our previous paper. we examined the usefulness of its predecessor the DSP48A1, for the generation of high-resolution delays. In this paper, we examine how the DSP48E1 has changed and what this means for the generation of high-resolution delays with this block.
Original language | English |
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Number of pages | 5 |
Publication status | Published - 30 Apr 2019 |
Event | International Conference on Digital Image & Signal Processing - Oxford, United Kingdom Duration: 29 Apr 2019 → 30 Apr 2019 |
Conference
Conference | International Conference on Digital Image & Signal Processing |
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Country/Territory | United Kingdom |
City | Oxford |
Period | 29/04/19 → 30/04/19 |
Keywords
- Time-to-Digital Converters
- Field Programmable Gate Arrays
- Xilinx
- Delay Generation
Fingerprint
Dive into the research topics of 'A 5.25ps-resolution TDC on FPGA using DSP blocks'. Together they form a unique fingerprint.Student Theses
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The Efficient Design of Time-to-Digital Converters
Author: Tancock, S., 2 Dec 2021Supervisor: Dahnoun, N. (Supervisor) & Rarity, J. (Supervisor)
Student thesis: Doctoral Thesis › Doctor of Philosophy (PhD)
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