A 5.25ps-resolution TDC on FPGA using DSP blocks

Scott Tancock; Naim Dahnoun

A 5.25ps-resolution TDC on FPGA using DSP blocks

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Abstract

With the introduction of its 7-series FPGAs, Xilinx introduced a new iteration of their DSP48 block, the DSP48E1. In our previous paper. we examined the usefulness of its predecessor the DSP48A1, for the generation of high-resolution delays. In this paper, we examine how the DSP48E1 has changed and what this means for the generation of high-resolution delays with this block.

Original language	English
Number of pages	5
Publication status	Published - 30 Apr 2019
Event	International Conference on Digital Image & Signal Processing - Oxford, United Kingdom Duration: 29 Apr 2019 → 30 Apr 2019

Conference

Conference	International Conference on Digital Image & Signal Processing
Country/Territory	United Kingdom
City	Oxford
Period	29/04/19 → 30/04/19

Keywords

Time-to-Digital Converters
Field Programmable Gate Arrays
Xilinx
Delay Generation

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The Efficient Design of Time-to-Digital Converters
Author: Tancock, S., 2 Dec 2021
Supervisor: Dahnoun, N. (Supervisor) & Rarity, J. (Supervisor)
Student thesis: Doctoral Thesis › Doctor of Philosophy (PhD)

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AU - Dahnoun, Naim

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N2 - With the introduction of its 7-series FPGAs, Xilinx introduced a new iteration of their DSP48 block, the DSP48E1. In our previous paper. we examined the usefulness of its predecessor the DSP48A1, for the generation of high-resolution delays. In this paper, we examine how the DSP48E1 has changed and what this means for the generation of high-resolution delays with this block.

AB - With the introduction of its 7-series FPGAs, Xilinx introduced a new iteration of their DSP48 block, the DSP48E1. In our previous paper. we examined the usefulness of its predecessor the DSP48A1, for the generation of high-resolution delays. In this paper, we examine how the DSP48E1 has changed and what this means for the generation of high-resolution delays with this block.

KW - Time-to-Digital Converters

KW - Field Programmable Gate Arrays

KW - Xilinx

KW - Delay Generation

M3 - Conference Paper

T2 - International Conference on Digital Image & Signal Processing

Y2 - 29 April 2019 through 30 April 2019

ER -

A 5.25ps-resolution TDC on FPGA using DSP blocks

Abstract

Conference

Keywords

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Student Theses

The Efficient Design of Time-to-Digital Converters

Cite this