A 5.25ps-resolution TDC on FPGA using DSP blocks

Scott Tancock; Naim Dahnoun

A 5.25ps-resolution TDC on FPGA using DSP blocks

Research output: Contribution to conference › Conference Paper › peer-review

53 Downloads (Pure)

Abstract

With the introduction of its 7-series FPGAs, Xilinx introduced a new iteration of their DSP48 block, the DSP48E1. In our previous paper. we examined the usefulness of its predecessor the DSP48A1, for the generation of high-resolution delays. In this paper, we examine how the DSP48E1 has changed and what this means for the generation of high-resolution delays with this block.

Original language	English
Number of pages	5
Publication status	Published - 30 Apr 2019
Event	International Conference on Digital Image & Signal Processing - Oxford, United Kingdom Duration: 29 Apr 2019 → 30 Apr 2019

Conference

Conference	International Conference on Digital Image & Signal Processing
Country	United Kingdom
City	Oxford
Period	29/04/19 → 30/04/19

Keywords

Time-to-Digital Converters
Field Programmable Gate Arrays
Xilinx
Delay Generation

Access to Document

Full-text PDF (accepted author manuscript)Accepted author manuscript, 248 KB

Fingerprint Dive into the research topics of 'A 5.25ps-resolution TDC on FPGA using DSP blocks'. Together they form a unique fingerprint.

Cite this

@conference{7859ed0af9614601ad360afdd9a9d06f,

title = "A 5.25ps-resolution TDC on FPGA using DSP blocks",

abstract = "With the introduction of its 7-series FPGAs, Xilinx introduced a new iteration of their DSP48 block, the DSP48E1. In our previous paper. we examined the usefulness of its predecessor the DSP48A1, for the generation of high-resolution delays. In this paper, we examine how the DSP48E1 has changed and what this means for the generation of high-resolution delays with this block.",

keywords = "Time-to-Digital Converters, Field Programmable Gate Arrays, Xilinx, Delay Generation",

author = "Scott Tancock and Naim Dahnoun",

year = "2019",

month = apr,

day = "30",

language = "English",

note = "International Conference on Digital Image & Signal Processing ; Conference date: 29-04-2019 Through 30-04-2019",

}

TY - CONF

T1 - A 5.25ps-resolution TDC on FPGA using DSP blocks

AU - Tancock, Scott

AU - Dahnoun, Naim

PY - 2019/4/30

Y1 - 2019/4/30

N2 - With the introduction of its 7-series FPGAs, Xilinx introduced a new iteration of their DSP48 block, the DSP48E1. In our previous paper. we examined the usefulness of its predecessor the DSP48A1, for the generation of high-resolution delays. In this paper, we examine how the DSP48E1 has changed and what this means for the generation of high-resolution delays with this block.

AB - With the introduction of its 7-series FPGAs, Xilinx introduced a new iteration of their DSP48 block, the DSP48E1. In our previous paper. we examined the usefulness of its predecessor the DSP48A1, for the generation of high-resolution delays. In this paper, we examine how the DSP48E1 has changed and what this means for the generation of high-resolution delays with this block.

KW - Time-to-Digital Converters

KW - Field Programmable Gate Arrays

KW - Xilinx

KW - Delay Generation

M3 - Conference Paper

T2 - International Conference on Digital Image & Signal Processing

Y2 - 29 April 2019 through 30 April 2019

ER -