This work presents a programmable, configurable motion estimation processor for the H.264 video coding standard, capable of handling the processing requirements of high definition (HD) video and suitable for FPGA implementation. The programmable aspect of the processor follows the ASIP (Application Specific Instruction set Processor) approach with a instruction set targeted to accelerating block matching motion estimation algorithms. Configurability relates to the ability to optimize the microarchitecture for the selected algorithm and performance requirements through varying the number and type of execution units at compile time.
|Translated title of the contribution||A configurable and programmable motion estimation processor for the H.264 video codec|
|Title of host publication||International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany|
|Pages||149 - 154|
|Number of pages||6|
|Publication status||Published - 8 Sep 2008|