A configurable and programmable motion estimation processor for the H.264 video codec

JL Nunez-Yanez, H Eddie, V Chouliaras

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

17 Citations (Scopus)

Abstract

This work presents a programmable, configurable motion estimation processor for the H.264 video coding standard, capable of handling the processing requirements of high definition (HD) video and suitable for FPGA implementation. The programmable aspect of the processor follows the ASIP (Application Specific Instruction set Processor) approach with a instruction set targeted to accelerating block matching motion estimation algorithms. Configurability relates to the ability to optimize the microarchitecture for the selected algorithm and performance requirements through varying the number and type of execution units at compile time.
Translated title of the contributionA configurable and programmable motion estimation processor for the H.264 video codec
Original languageEnglish
Title of host publicationInternational Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany
Pages149 - 154
Number of pages6
DOIs
Publication statusPublished - 8 Sep 2008

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