A configurable and programmable motion estimation processor for the H.264 video codec

JL Nunez-Yanez; H Eddie; V Chouliaras

doi:10.1109/FPL.2008.4629923

A configurable and programmable motion estimation processor for the H.264 video codec

JL Nunez-Yanez, H Eddie, V Chouliaras

Department of Electrical & Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

17 Citations (Scopus)

Abstract

This work presents a programmable, configurable motion estimation processor for the H.264 video coding standard, capable of handling the processing requirements of high definition (HD) video and suitable for FPGA implementation. The programmable aspect of the processor follows the ASIP (Application Specific Instruction set Processor) approach with a instruction set targeted to accelerating block matching motion estimation algorithms. Configurability relates to the ability to optimize the microarchitecture for the selected algorithm and performance requirements through varying the number and type of execution units at compile time.

Translated title of the contribution	A configurable and programmable motion estimation processor for the H.264 video codec
Original language	English
Title of host publication	International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany
Pages	149 - 154
Number of pages	6
DOIs	https://doi.org/10.1109/FPL.2008.4629923
Publication status	Published - 8 Sept 2008

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abstract = "This work presents a programmable, configurable motion estimation processor for the H.264 video coding standard, capable of handling the processing requirements of high definition (HD) video and suitable for FPGA implementation. The programmable aspect of the processor follows the ASIP (Application Specific Instruction set Processor) approach with a instruction set targeted to accelerating block matching motion estimation algorithms. Configurability relates to the ability to optimize the microarchitecture for the selected algorithm and performance requirements through varying the number and type of execution units at compile time.",

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AB - This work presents a programmable, configurable motion estimation processor for the H.264 video coding standard, capable of handling the processing requirements of high definition (HD) video and suitable for FPGA implementation. The programmable aspect of the processor follows the ASIP (Application Specific Instruction set Processor) approach with a instruction set targeted to accelerating block matching motion estimation algorithms. Configurability relates to the ability to optimize the microarchitecture for the selected algorithm and performance requirements through varying the number and type of execution units at compile time.

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DO - 10.1109/FPL.2008.4629923

M3 - Conference Contribution (Conference Proceeding)

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BT - International Conference on Field Programmable Logic and Applications (FPL 2008), Heidelberg, Germany

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A configurable and programmable motion estimation processor for the H.264 video codec

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