We address routing in Networks-On-Chip (NoC) architectures that use irregular mesh topologies with Long-Range Links (LRL). These topologies create difficult conditions for routing algorithms, as standard algorithms assume a static, regular link structure and exploit the uniformity of regular meshes to avoid deadlock and maintain routability. We present a novel routing algorithm that can cope with these irregular topologies and adapt to run-time LRL insertion and topology reconfiguration. Our approach to accommodate dynamic topology reconfiguration is to use a new technique that decomposes routing relations into two stages: the calculation of output ports on the current minimal path and the application of routing restrictions designed to prevent deadlock. In addition, we present a selection function that uses local topology data to adaptively select optimal paths. The routing algorithm is shown to be deadlock-free, after which an analysis of all possible routing decisions in the region of an LRL is carried out. We show that the routing algorithm minimises the cost of sub-optimally placed LRL and display the hop savings available. When applied to LRLs of less than seven hops, the overall traffic hop count and associated routing energy cost is reduced. In a simulated 8 × 8 network the total input buffer usage across the network was reduced by 6.5%.
|Translated title of the contribution||A Deadlock-free Routing Algorithm for Dynamically Reconfigurable Networks-on-Chip|
|Number of pages||32|
|Journal||Microprocessors and Microsystems|
|Publication status||Published - Sep 2010|
Bibliographical notePublisher: Elsevier
Jackson, C. R., & Hollis, SJ. (2010). A Deadlock-free Routing Algorithm for Dynamically Reconfigurable Networks-on-Chip. Microprocessors and Microsystems, 35(2), 139-151. https://doi.org/10.1016/j.micpro.2010.09.004