A DSOGI-FLL-based Dead-Time Elimination PWM for Three-Phase Power Converters

The dead-time elimination pulse width modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead-time and essentially avoiding the dead-time effect in power converters. However, the current zero-crossing will be distorted by the current jump generated by the drive-pulse alternation. And the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is therefore proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pluses to smooth the current jump at zero-crossing. And a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments respectively in the unbalanced-current, power-change, and frequency-variation conditions with a RL load, as well as in a grid-connected converter.