A Fault-tolerant Voter Circuit in NEM Technology

Dominik Rudolf, Ardavan Elahi, Axel Jantsch, I D B Pamunuwa

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

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Abstract

Circuits implemented with micro- and nano-electromechanical (MEM/NEM) relays have the benefit of being capable of operating in environments with high temperature as well as high radiation levels. However, due to potential defects in the NEM relays, circuits using this technology exhibit poor reliability. To address this issue, design techniques that incorporate hardware redundancy are often implemented to improve reliability. A simple and well-established design technique in the domain of hardware redundancy is Triple Modular Redundancy(TMR). Systems with TMR perform a voting process on the outputs of replicated modules using a voting circuit. These voting circuits are usually unreliable because they are also susceptible to physical defects. Therefore, various voter designs have been proposed to increase the reliability of the voting circuit. However, conventional voter designs often fail when provided with inputs at undefined logic levels or significantly increase hardware overhead due to their high device count. This paper proposes a novel voter design utilizing NEM technology, leveraging the functionalities of NEM-based relays. Besides tolerating single faulty inputs, the voter can also handle single inputs at an undefined logic level. Experimental results based on digital simulations show that the proposed voter achieves a 72% reduction in device count compared to the best-performing conventional voter design investigated, while maintaining a similar level of fault tolerance.
Original languageEnglish
Title of host publicationIEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages6
ISBN (Electronic)9798331514891
ISBN (Print)9798331514907
DOIs
Publication statusPublished - 25 Nov 2025
EventDFT 2025: 38th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems - Barcelona, Barcelona, Spain
Duration: 21 Oct 202523 Oct 2025
http://www.dfts.org/

Publication series

NameIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
PublisherIEEE
ISSN (Print)2765-933X
ISSN (Electronic)2576-1501

Conference

ConferenceDFT 2025: 38th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Country/TerritorySpain
CityBarcelona
Period21/10/2523/10/25
Internet address

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