A flexible test-bed for developing hybrid linear transmitter architectures

SI Mann, MA Beach, PA Warr, JP McGeehan

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

3 Citations (Scopus)
352 Downloads (Pure)


The focus of this paper is a digital test-bed that accommodates flexibility in the designing of hybrid architectures. It comprises a high-speed analog-to-digital and digital-to-analog interface, an FPGA and a C6x DSP evaluation board for signal-processing. The remainder of the test-bed comprises a RF transmitter. The modular nature of the test-bed allows it to support either quadrature baseband or digital IF sampling. The use of a FPGA and DSP for digital processing allows high throughput whilst allowing complex linearisation algorithms. The test bed performance is demonstrated using the Cartesian loop transmitter architecture. The Cartesian loop was chosen as it is a well known linear transmitter architecture. Further work will be to include two or more architectures to raise the efficiency and performance (greater linearity or bandwidth). The candidate schemes for hybrid architectures with Cartesian loop are pre-distortion, envelope elimination and restoration and dynamic biasing.
Translated title of the contributionA Flexible Test-Bed for Developing Hybrid Linear Transmitter Architectures
Original languageEnglish
Title of host publicationIEEE 53rd Vehicular Technology Conference, Rhodes, Spring 2001, Proceedings CD ROM:IEEE catalogue No.01CH37202C
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1983 - 1986
ISBN (Print)0780367286
Publication statusPublished - May 2001
Event53rd Vehicular Technology Conference 2001 (VTC 2001-Spring) - Rhodes, Greece
Duration: 1 May 2001 → …


Conference53rd Vehicular Technology Conference 2001 (VTC 2001-Spring)
Period1/05/01 → …

Bibliographical note

Other: ISBN:07803-6730-8
Rose publication type: Conference contribution

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