A flexible test-bed for developing hybrid linear transmitter architectures

SI Mann; MA Beach; PA Warr; JP McGeehan

doi:10.1109/VETECS.2001.945043

A flexible test-bed for developing hybrid linear transmitter architectures

SI Mann, MA Beach, PA Warr, JP McGeehan

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

3 Citations (Scopus)

383 Downloads (Pure)

Abstract

The focus of this paper is a digital test-bed that accommodates flexibility in the designing of hybrid architectures. It comprises a high-speed analog-to-digital and digital-to-analog interface, an FPGA and a C6x DSP evaluation board for signal-processing. The remainder of the test-bed comprises a RF transmitter. The modular nature of the test-bed allows it to support either quadrature baseband or digital IF sampling. The use of a FPGA and DSP for digital processing allows high throughput whilst allowing complex linearisation algorithms. The test bed performance is demonstrated using the Cartesian loop transmitter architecture. The Cartesian loop was chosen as it is a well known linear transmitter architecture. Further work will be to include two or more architectures to raise the efficiency and performance (greater linearity or bandwidth). The candidate schemes for hybrid architectures with Cartesian loop are pre-distortion, envelope elimination and restoration and dynamic biasing.

Translated title of the contribution	A Flexible Test-Bed for Developing Hybrid Linear Transmitter Architectures
Original language	English
Title of host publication	IEEE 53rd Vehicular Technology Conference, Rhodes, Spring 2001, Proceedings CD ROM:IEEE catalogue No.01CH37202C
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1983 - 1986
Volume	3
ISBN (Print)	0780367286
DOIs	https://doi.org/10.1109/VETECS.2001.945043
Publication status	Published - May 2001
Event	53rd Vehicular Technology Conference 2001 (VTC 2001-Spring) - Rhodes, Greece Duration: 1 May 2001 → …

Conference

Conference	53rd Vehicular Technology Conference 2001 (VTC 2001-Spring)
Country/Territory	Greece
City	Rhodes
Period	1/05/01 → …

Bibliographical note

Other: ISBN:07803-6730-8
Rose publication type: Conference contribution

Terms of use: Copyright © 2001 IEEE. Reprinted from Proceedings of IEEE Vehicular Technology Conference, Spring 2001. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected].

By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

Keywords

cellular radio

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10.1109/VETECS.2001.945043

Mann IEEE VTC Spring 2001Accepted author manuscript, 613 KB

http://hdl.handle.net/1983/264

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Mann, SI., Beach, MA., Warr, PA., & McGeehan, JP. (2001). A flexible test-bed for developing hybrid linear transmitter architectures. In IEEE 53rd Vehicular Technology Conference, Rhodes, Spring 2001, Proceedings CD ROM:IEEE catalogue No.01CH37202C (Vol. 3, pp. 1983 - 1986). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/VETECS.2001.945043

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Mann, SI, Beach, MA , Warr, PA & McGeehan, JP 2001, A flexible test-bed for developing hybrid linear transmitter architectures. in IEEE 53rd Vehicular Technology Conference, Rhodes, Spring 2001, Proceedings CD ROM:IEEE catalogue No.01CH37202C. vol. 3, Institute of Electrical and Electronics Engineers (IEEE), pp. 1983 - 1986, 53rd Vehicular Technology Conference 2001 (VTC 2001-Spring), Rhodes, Greece, 1/05/01. https://doi.org/10.1109/VETECS.2001.945043

A flexible test-bed for developing hybrid linear transmitter architectures. / Mann, SI; Beach, MA ; Warr, PA et al.
IEEE 53rd Vehicular Technology Conference, Rhodes, Spring 2001, Proceedings CD ROM:IEEE catalogue No.01CH37202C. Vol. 3 Institute of Electrical and Electronics Engineers (IEEE), 2001. p. 1983 - 1986.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

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N2 - The focus of this paper is a digital test-bed that accommodates flexibility in the designing of hybrid architectures. It comprises a high-speed analog-to-digital and digital-to-analog interface, an FPGA and a C6x DSP evaluation board for signal-processing. The remainder of the test-bed comprises a RF transmitter. The modular nature of the test-bed allows it to support either quadrature baseband or digital IF sampling. The use of a FPGA and DSP for digital processing allows high throughput whilst allowing complex linearisation algorithms. The test bed performance is demonstrated using the Cartesian loop transmitter architecture. The Cartesian loop was chosen as it is a well known linear transmitter architecture. Further work will be to include two or more architectures to raise the efficiency and performance (greater linearity or bandwidth). The candidate schemes for hybrid architectures with Cartesian loop are pre-distortion, envelope elimination and restoration and dynamic biasing.

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T2 - 53rd Vehicular Technology Conference 2001 (VTC 2001-Spring)

Y2 - 1 May 2001

ER -

A flexible test-bed for developing hybrid linear transmitter architectures

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Keywords

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