The focus of this paper is a digital test-bed that accommodates flexibility in the designing of hybrid architectures. It comprises a high-speed analog-to-digital and digital-to-analog interface, an FPGA and a C6x DSP evaluation board for signal-processing. The remainder of the test-bed comprises a RF transmitter. The modular nature of the test-bed allows it to support either quadrature baseband or digital IF sampling. The use of a FPGA and DSP for digital processing allows high throughput whilst allowing complex linearisation algorithms. The test bed performance is demonstrated using the Cartesian loop transmitter architecture. The Cartesian loop was chosen as it is a well known linear transmitter architecture. Further work will be to include two or more architectures to raise the efficiency and performance (greater linearity or bandwidth). The candidate schemes for hybrid architectures with Cartesian loop are pre-distortion, envelope elimination and restoration and dynamic biasing.
|Translated title of the contribution||A Flexible Test-Bed for Developing Hybrid Linear Transmitter Architectures|
|Title of host publication||IEEE 53rd Vehicular Technology Conference, Rhodes, Spring 2001, Proceedings CD ROM:IEEE catalogue No.01CH37202C|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Pages||1983 - 1986|
|Publication status||Published - May 2001|
|Event||53rd Vehicular Technology Conference 2001 (VTC 2001-Spring) - Rhodes, Greece|
Duration: 1 May 2001 → …
|Conference||53rd Vehicular Technology Conference 2001 (VTC 2001-Spring)|
|Period||1/05/01 → …|
Bibliographical noteOther: ISBN:07803-6730-8
Rose publication type: Conference contribution
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