A Global Wire Planning Scheme for Network-on-Chip

Jian Liu; L-R Zheng; Dinesh Pamunuwa; Hannu Tenhunen

doi:10.1109/ISCAS.2003.1206364

A Global Wire Planning Scheme for Network-on-Chip

Jian Liu, L-R Zheng, Dinesh Pamunuwa, Hannu Tenhunen

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

14 Citations (Scopus)

Abstract

As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed.

Original language	Undefined/Unknown
Title of host publication	Proc. IEEE International Symposium on Circuits and Systems, (ISCAS)
Pages	IV-892
Volume	4
DOIs	https://doi.org/10.1109/ISCAS.2003.1206364
Publication status	Published - 1 May 2003

Structured keywords

Photonics and Quantum

Keywords

integrated circuit design
integrated circuit interconnections
packet switching
global communication
global wire delay
global wire planning
interconnect
network-on-chip
packet switched architecture
Bandwidth
Communication switching
Delay
Global communication
Integrated circuit interconnections
Network topology
Network-on-a-chip
Packet switching
Switches
Wire

Access to Document

10.1109/ISCAS.2003.1206364

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Cite this

@inproceedings{d03d6554898341849f58cb9f7fbc09e6,

title = "A Global Wire Planning Scheme for Network-on-Chip",

abstract = "As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed.",

keywords = "integrated circuit design, integrated circuit interconnections, packet switching, global communication, global wire delay, global wire planning, interconnect, network-on-chip, packet switched architecture, Bandwidth, Communication switching, Delay, Global communication, Integrated circuit interconnections, Network topology, Network-on-a-chip, Packet switching, Switches, Wire",

author = "Jian Liu and L-R Zheng and Dinesh Pamunuwa and Hannu Tenhunen",

year = "2003",

month = may,

day = "1",

doi = "10.1109/ISCAS.2003.1206364",

language = "Undefined/Unknown",

volume = "4",

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booktitle = "Proc. IEEE International Symposium on Circuits and Systems, (ISCAS)",

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T1 - A Global Wire Planning Scheme for Network-on-Chip

AU - Liu, Jian

AU - Zheng, L-R

AU - Pamunuwa, Dinesh

AU - Tenhunen, Hannu

PY - 2003/5/1

Y1 - 2003/5/1

N2 - As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed.

AB - As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed.

KW - integrated circuit design

KW - integrated circuit interconnections

KW - packet switching

KW - global communication

KW - global wire delay

KW - global wire planning

KW - interconnect

KW - network-on-chip

KW - packet switched architecture

KW - Bandwidth

KW - Communication switching

KW - Delay

KW - Global communication

KW - Integrated circuit interconnections

KW - Network topology

KW - Network-on-a-chip

KW - Packet switching

KW - Switches

KW - Wire

U2 - 10.1109/ISCAS.2003.1206364

DO - 10.1109/ISCAS.2003.1206364

M3 - Conference Contribution (Conference Proceeding)

VL - 4

SP - IV-892

BT - Proc. IEEE International Symposium on Circuits and Systems, (ISCAS)

ER -