A Global Wire Planning Scheme for Network-on-Chip

Jian Liu, L-R Zheng, Dinesh Pamunuwa, Hannu Tenhunen

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

14 Citations (Scopus)


As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed.
Original languageUndefined/Unknown
Title of host publicationProc. IEEE International Symposium on Circuits and Systems, (ISCAS)
Publication statusPublished - 1 May 2003

Structured keywords

  • Photonics and Quantum


  • integrated circuit design
  • integrated circuit interconnections
  • packet switching
  • global communication
  • global wire delay
  • global wire planning
  • interconnect
  • network-on-chip
  • packet switched architecture
  • Bandwidth
  • Communication switching
  • Delay
  • Global communication
  • Integrated circuit interconnections
  • Network topology
  • Network-on-a-chip
  • Packet switching
  • Switches
  • Wire

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