A hybrid reliability assessment method and its support of sequential logic modelling

Samuel N. Pagliarini, Lirida A B De Naviner, Jean Francois Naviner, Dhiraj Pradhan

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.

Original languageEnglish
Title of host publicationProceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014
PublisherIEEE Computer Society
Pages182-183
Number of pages2
ISBN (Print)9781479953233
DOIs
Publication statusPublished - 2014
Event20th IEEE International On-Line Testing Symposium, IOLTS 2014 - Catalunya, Spain
Duration: 7 Jul 20149 Jul 2014

Conference

Conference20th IEEE International On-Line Testing Symposium, IOLTS 2014
CountrySpain
CityCatalunya
Period7/07/149/07/14

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