A hybrid reliability assessment method and its support of sequential logic modelling

Samuel N. Pagliarini; Lirida A B De Naviner; Jean Francois Naviner; Dhiraj Pradhan

doi:10.1109/IOLTS.2014.6873690

A hybrid reliability assessment method and its support of sequential logic modelling

Samuel N. Pagliarini, Lirida A B De Naviner, Jean Francois Naviner, Dhiraj Pradhan

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Abstract

This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.

Original language	English
Title of host publication	Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014
Publisher	IEEE Computer Society
Pages	182-183
Number of pages	2
ISBN (Print)	9781479953233
DOIs	https://doi.org/10.1109/IOLTS.2014.6873690
Publication status	Published - 2014
Event	20th IEEE International On-Line Testing Symposium, IOLTS 2014 - Catalunya, Spain Duration: 7 Jul 2014 → 9 Jul 2014

Conference

Conference	20th IEEE International On-Line Testing Symposium, IOLTS 2014
Country/Territory	Spain
City	Catalunya
Period	7/07/14 → 9/07/14

Access to Document

10.1109/IOLTS.2014.6873690

Handle.net

Persistent link

Cite this

@inproceedings{4181fde0efc34c9e8b15f7c5a5a6c357,

title = "A hybrid reliability assessment method and its support of sequential logic modelling",

abstract = "This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.",

author = "Pagliarini, {Samuel N.} and {De Naviner}, {Lirida A B} and Naviner, {Jean Francois} and Dhiraj Pradhan",

year = "2014",

doi = "10.1109/IOLTS.2014.6873690",

language = "English",

isbn = "9781479953233",

pages = "182--183",

booktitle = "Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014",

publisher = "IEEE Computer Society",

address = "United States",

note = "20th IEEE International On-Line Testing Symposium, IOLTS 2014 ; Conference date: 07-07-2014 Through 09-07-2014",

}

Pagliarini, SN, De Naviner, LAB, Naviner, JF & Pradhan, D 2014, A hybrid reliability assessment method and its support of sequential logic modelling. in Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014., 6873690, IEEE Computer Society, pp. 182-183, 20th IEEE International On-Line Testing Symposium, IOLTS 2014, Catalunya, Spain, 7/07/14. https://doi.org/10.1109/IOLTS.2014.6873690

A hybrid reliability assessment method and its support of sequential logic modelling. / Pagliarini, Samuel N.; De Naviner, Lirida A B; Naviner, Jean Francois et al.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014. IEEE Computer Society, 2014. p. 182-183 6873690.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - A hybrid reliability assessment method and its support of sequential logic modelling

AU - Pagliarini, Samuel N.

AU - De Naviner, Lirida A B

AU - Naviner, Jean Francois

AU - Pradhan, Dhiraj

PY - 2014

Y1 - 2014

N2 - This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.

AB - This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.

UR - http://www.scopus.com/inward/record.url?scp=84906656840&partnerID=8YFLogxK

U2 - 10.1109/IOLTS.2014.6873690

DO - 10.1109/IOLTS.2014.6873690

M3 - Conference Contribution (Conference Proceeding)

AN - SCOPUS:84906656840

SN - 9781479953233

SP - 182

EP - 183

BT - Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014

PB - IEEE Computer Society

T2 - 20th IEEE International On-Line Testing Symposium, IOLTS 2014

Y2 - 7 July 2014 through 9 July 2014

ER -

A hybrid reliability assessment method and its support of sequential logic modelling

Abstract

Conference

Access to Document

Handle.net

Other files and links

Fingerprint

PROCESS VARIATION AWARE SYNTHESIS OF NANO-CMOS CIRCUITS

Cite this

A hybrid reliability assessment method and its support of sequential logic modelling

Abstract

Conference

Access to Document

Handle.net

Other files and links

Fingerprint

Projects

PROCESS VARIATION AWARE SYNTHESIS OF NANO-CMOS CIRCUITS

Cite this