A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes over GF(2m)

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan

Research output: Contribution to journalArticle (Academic Journal)

1 Citation (Scopus)

Abstract

This paper presents a novel low-complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF 2m. For an m input circuit, the proposed scheme can correct m≤ Dw≤ 3m/2-1 multiple error combinations out of all the possible 2m-1 errors, which is superior to many existing approaches. From the mathematical and practical evaluations, the best case error correction is m/2 bit errors. Tests on 80-bit parallel and, for the first time, on 163-bit Federal Information Processing Standard/National Institute of Standards and Technology (FIPS/NIST) standard word-level Galois field (GF) multipliers, suggest that it requires only 106% and 170% area overheads, respectively, which is lower than the existing approaches, while error injection-based behavioral analysis demonstrates its wider error correction capability.

Original languageEnglish
Article number6876030
Pages (from-to)1448-1458
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number8
DOIs
Publication statusPublished - 1 Aug 2015

Keywords

  • Application specific integrated circuits (ASICs)
  • Bose-Choudhury-Hocquenghem (BCH) code
  • error correction circuit (ECC)
  • Galois field (GF)
  • multiple event upsets (MEUs)
  • radiation hardening
  • simple parity
  • single event upsets (SEUs)
  • VLSI

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