A multi-standard video encoding coprocessor is presented that efficiently accelerates MPEG-2, MPEG-4 (XViD) and a proprietary H.264 encoder. The proposed architecture attaches to a configurable, extensible RISC CPU to form a highly efficient solution to the computational complexity of current and emerging video coding standards. A subset of the ISA has been implemented as a VLSI macrocell for a high performance 0.13 /spl mu/m silicon process.
|Translated title of the contribution||A multi-standard video accelerator based on a vector architecture|
|Pages (from-to)||160 - 167|
|Number of pages||8|
|Journal||IEEE Transactions on Consumer Electronics|
|Publication status||Published - Feb 2005|
Bibliographical notePublisher: Institute of Electrical and Electronics Engineers (IEEE)
Chouliaras, VA., Nunez-Yanez, JL., Rovati, F., & Alfonso, D. (2005). A multi-standard video accelerator based on a vector architecture. IEEE Transactions on Consumer Electronics, 51 (1), 160 - 167. https://doi.org/10.1109/TCE.2005.1405714