A multi-standard video accelerator based on a vector architecture

VA Chouliaras, JL Nunez-Yanez, F Rovati, D Alfonso

Research output: Contribution to journalArticle (Academic Journal)

13 Citations (Scopus)

Abstract

A multi-standard video encoding coprocessor is presented that efficiently accelerates MPEG-2, MPEG-4 (XViD) and a proprietary H.264 encoder. The proposed architecture attaches to a configurable, extensible RISC CPU to form a highly efficient solution to the computational complexity of current and emerging video coding standards. A subset of the ISA has been implemented as a VLSI macrocell for a high performance 0.13 /spl mu/m silicon process.
Translated title of the contributionA multi-standard video accelerator based on a vector architecture
Original languageEnglish
Pages (from-to)160 - 167
Number of pages8
JournalIEEE Transactions on Consumer Electronics
Volume51 (1)
DOIs
Publication statusPublished - Feb 2005

Bibliographical note

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

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