A multi-standard video accelerator based on a vector architecture

VA Chouliaras; JL Nunez-Yanez; F Rovati; D Alfonso

doi:10.1109/TCE.2005.1405714

A multi-standard video accelerator based on a vector architecture

VA Chouliaras, JL Nunez-Yanez, F Rovati, D Alfonso

Research output: Contribution to journal › Article (Academic Journal) › peer-review

13 Citations (Scopus)

Abstract

A multi-standard video encoding coprocessor is presented that efficiently accelerates MPEG-2, MPEG-4 (XViD) and a proprietary H.264 encoder. The proposed architecture attaches to a configurable, extensible RISC CPU to form a highly efficient solution to the computational complexity of current and emerging video coding standards. A subset of the ISA has been implemented as a VLSI macrocell for a high performance 0.13 /spl mu/m silicon process.

Translated title of the contribution	A multi-standard video accelerator based on a vector architecture
Original language	English
Pages (from-to)	160 - 167
Number of pages	8
Journal	IEEE Transactions on Consumer Electronics
Volume	51 (1)
DOIs	https://doi.org/10.1109/TCE.2005.1405714
Publication status	Published - Feb 2005

Bibliographical note

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

Access to Document

10.1109/TCE.2005.1405714

http://ieeexplore.ieee.org/search/srchabstract.jsp?arnumber=1405714&isnumber=30482&punumber=30&k2dockey=1405714@ieeejrns&query=%28+%28+nunez%3Cin%3Emetadata+%29+%29+%3Cand%3E+%28pyr+%3E%3D+2003+%3Cand%3E+pyr+%3C%3D+2006%29&pos=15

Handle.net

Persistent link

Cite this

@article{75afd4d717f941f9b6f0ce4c8e7cd032,

title = "A multi-standard video accelerator based on a vector architecture",

abstract = "A multi-standard video encoding coprocessor is presented that efficiently accelerates MPEG-2, MPEG-4 (XViD) and a proprietary H.264 encoder. The proposed architecture attaches to a configurable, extensible RISC CPU to form a highly efficient solution to the computational complexity of current and emerging video coding standards. A subset of the ISA has been implemented as a VLSI macrocell for a high performance 0.13 /spl mu/m silicon process.",

author = "VA Chouliaras and JL Nunez-Yanez and F Rovati and D Alfonso",

note = "Publisher: Institute of Electrical and Electronics Engineers (IEEE)",

year = "2005",

month = feb,

doi = "10.1109/TCE.2005.1405714",

language = "English",

volume = "51 (1)",

pages = "160 -- 167",

journal = "IEEE Transactions on Consumer Electronics",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

}

TY - JOUR

T1 - A multi-standard video accelerator based on a vector architecture

AU - Chouliaras, VA

AU - Nunez-Yanez, JL

AU - Rovati, F

AU - Alfonso, D

N1 - Publisher: Institute of Electrical and Electronics Engineers (IEEE)

PY - 2005/2

Y1 - 2005/2

N2 - A multi-standard video encoding coprocessor is presented that efficiently accelerates MPEG-2, MPEG-4 (XViD) and a proprietary H.264 encoder. The proposed architecture attaches to a configurable, extensible RISC CPU to form a highly efficient solution to the computational complexity of current and emerging video coding standards. A subset of the ISA has been implemented as a VLSI macrocell for a high performance 0.13 /spl mu/m silicon process.

AB - A multi-standard video encoding coprocessor is presented that efficiently accelerates MPEG-2, MPEG-4 (XViD) and a proprietary H.264 encoder. The proposed architecture attaches to a configurable, extensible RISC CPU to form a highly efficient solution to the computational complexity of current and emerging video coding standards. A subset of the ISA has been implemented as a VLSI macrocell for a high performance 0.13 /spl mu/m silicon process.

U2 - 10.1109/TCE.2005.1405714

DO - 10.1109/TCE.2005.1405714

M3 - Article (Academic Journal)

VL - 51 (1)

SP - 160

EP - 167

JO - IEEE Transactions on Consumer Electronics

JF - IEEE Transactions on Consumer Electronics

ER -

A multi-standard video accelerator based on a vector architecture

Abstract

Bibliographical note

Access to Document

Handle.net

Fingerprint

Cite this