A new circuit topology for floating high voltage level shifters

Dawei Liu, Simon J Hollis, Bernard H Stark

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

5 Citations (Scopus)

Abstract

A novel and simple circuit topology is presented for high-speed, floating, high voltage level shifters. It uses a current mirror plus latch circuit composed of two inverters. Simulations based on AMS 0.18 μm High Voltage (HV) CMOS Technology show this circuit to combine high speed, low power dissipation, and small layout area. The simulation results show the propagation delay to be below 150 ps for a transition from 1.8 V to 13.8 V.

Original languageEnglish
Title of host publicationConference Proceedings - 10th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2014
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISBN (Electronic)9781479949946
Publication statusPublished - 1 Jan 2014
Event10th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2014 - Grenoble, France
Duration: 29 Jun 20143 Jul 2014

Conference

Conference10th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2014
CountryFrance
CityGrenoble
Period29/06/143/07/14

Keywords

  • BCD
  • Floating
  • High speed
  • High voltage
  • HV CMOS
  • Level shifter
  • Low power

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