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Abstract
A novel and simple circuit topology is presented for high-speed, floating, high voltage level shifters. It uses a current mirror plus latch circuit composed of two inverters. Simulations based on AMS 0.18 μm High Voltage (HV) CMOS Technology show this circuit to combine high speed, low power dissipation, and small layout area. The simulation results show the propagation delay to be below 150 ps for a transition from 1.8 V to 13.8 V.
Original language | English |
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Title of host publication | Conference Proceedings - 10th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2014 |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
ISBN (Electronic) | 9781479949946 |
Publication status | Published - 1 Jan 2014 |
Event | 10th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2014 - Grenoble, France Duration: 29 Jun 2014 → 3 Jul 2014 |
Conference
Conference | 10th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2014 |
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Country/Territory | France |
City | Grenoble |
Period | 29/06/14 → 3/07/14 |
Keywords
- BCD
- Floating
- High speed
- High voltage
- HV CMOS
- Level shifter
- Low power
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Dive into the research topics of 'A new circuit topology for floating high voltage level shifters'. Together they form a unique fingerprint.Projects
- 1 Finished
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Pulse quietening at source for higher-frequency power and signal switching
Dalton, J. J. O. (Researcher), Dymond, H. C. P. (Researcher), Liu, D. (Researcher), McNeill, J. N. (Co-Principal Investigator), Pamunuwa, I. D. B. (Co-Principal Investigator), Wang, J. (Researcher), Hollis, S. (Co-Principal Investigator) & Stark, B. H. (Principal Investigator)
17/06/13 → 16/06/18
Project: Research