A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application

Singh Jawar, [No Value] K. Ramakrishnan, Mookerjea S., Datta S., Narayanan V., Dhiraj Pradhan

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Translated title of the contributionA Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application
Original languageEnglish
Title of host publicationTo appear in the proceedings of 15th Asia South Pacific Design Automation Conference (ASPDAC), January, Taipei, Taiwan, 2010
Publication statusPublished - 2010

Bibliographical note

Other page information: -
Conference Proceedings/Title of Journal: To appear in the proceedings of 15th Asia South Pacific Design Automation Conference (ASPDAC), January, Taipei, Taiwan, 2010
Other identifier: 2001093

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