A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application

Singh Jawar; K Ramakrishnan; S Mookerjea; S Datta; Vijaykrishnan Narayanan; Dhiraj Pradhan

doi:10.1109/ASPDAC.2010.5419897

A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application

Singh Jawar, K Ramakrishnan, S Mookerjea, S Datta, Vijaykrishnan Narayanan, Dhiraj Pradhan

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

92 Citations (Scopus)

Translated title of the contribution	A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application
Original language	English
Title of host publication	2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
DOIs	https://doi.org/10.1109/ASPDAC.2010.5419897
Publication status	Published - 2010

Bibliographical note

Other page information: -
Conference Proceedings/Title of Journal: To appear in the proceedings of 15th Asia South Pacific Design Automation Conference (ASPDAC), January, Taipei, Taiwan, 2010
Other identifier: 2001093

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10.1109/ASPDAC.2010.5419897

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Cite this

@inproceedings{5928ced12c054bab9479fa9907eb5308,

title = "A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application",

author = "Singh Jawar and K Ramakrishnan and S Mookerjea and S Datta and Vijaykrishnan Narayanan and Dhiraj Pradhan",

note = "Other page information: - Conference Proceedings/Title of Journal: To appear in the proceedings of 15th Asia South Pacific Design Automation Conference (ASPDAC), January, Taipei, Taiwan, 2010 Other identifier: 2001093",

year = "2010",

doi = "10.1109/ASPDAC.2010.5419897",

language = "English",

booktitle = "2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application. / Jawar, Singh; Ramakrishnan, K; Mookerjea, S et al.
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC). Institute of Electrical and Electronics Engineers (IEEE), 2010.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - A Novel Si-Tunnel FET SRAM Design for Ultra Low-Power 0.3V VDD Application

AU - Jawar, Singh

AU - Ramakrishnan, K

AU - Mookerjea, S

AU - Datta, S

AU - Narayanan, Vijaykrishnan

AU - Pradhan, Dhiraj

N1 - Other page information: - Conference Proceedings/Title of Journal: To appear in the proceedings of 15th Asia South Pacific Design Automation Conference (ASPDAC), January, Taipei, Taiwan, 2010 Other identifier: 2001093

PY - 2010

Y1 - 2010

U2 - 10.1109/ASPDAC.2010.5419897

DO - 10.1109/ASPDAC.2010.5419897

M3 - Conference Contribution (Conference Proceeding)

BT - 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -