| Translated title of the contribution | A Novel Soft Error Tolerant Low Power RAM Architecture |
|---|---|
| Original language | English |
| Title of host publication | 20th annual symposium on Integrated circuits and system design SBCCI '07 |
| Publication status | Published - 2007 |
Bibliographical note
Other page information: -Conference Proceedings/Title of Journal: 20th annual symposium on Integrated circuits and system design SBCCI '07
Other identifier: 2000730
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