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Abstract
This paper proposes a fault-aware placement strategy for digital circuits. Placement algorithms usually have a goal of reducing the overall chip area and routing wirelength while the solution proposed in this paper focuses on reducing the effects of multiple faults caused by transients. The target circuits are properly analysed in order to identify scenarios that promote reductions in the overall error rate. The occurrence of these scenarios is then maximised when the proposed placement strategy is executed. Results show that substantial error rate reductions can be achieved.
Original language | English |
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Title of host publication | Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014 |
Publisher | IEEE Computer Society |
Pages | 69-74 |
Number of pages | 6 |
ISBN (Print) | 9781479953233 |
DOIs | |
Publication status | Published - 2014 |
Event | 20th IEEE International On-Line Testing Symposium, IOLTS 2014 - Catalunya, Spain Duration: 7 Jul 2014 → 9 Jul 2014 |
Conference
Conference | 20th IEEE International On-Line Testing Symposium, IOLTS 2014 |
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Country/Territory | Spain |
City | Catalunya |
Period | 7/07/14 → 9/07/14 |
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Dive into the research topics of 'A placement strategy for reducing the effects of multiple faults in digital circuits'. Together they form a unique fingerprint.Projects
- 1 Finished
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PROCESS VARIATION AWARE SYNTHESIS OF NANO-CMOS CIRCUITS
Pradhan, D. K. (Principal Investigator)
1/10/09 → 1/03/13
Project: Research