A placement strategy for reducing the effects of multiple faults in digital circuits

Samuel N. Pagliarini, Dhiraj Pradhan

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

9 Citations (Scopus)

Abstract

This paper proposes a fault-aware placement strategy for digital circuits. Placement algorithms usually have a goal of reducing the overall chip area and routing wirelength while the solution proposed in this paper focuses on reducing the effects of multiple faults caused by transients. The target circuits are properly analysed in order to identify scenarios that promote reductions in the overall error rate. The occurrence of these scenarios is then maximised when the proposed placement strategy is executed. Results show that substantial error rate reductions can be achieved.

Original languageEnglish
Title of host publicationProceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014
PublisherIEEE Computer Society
Pages69-74
Number of pages6
ISBN (Print)9781479953233
DOIs
Publication statusPublished - 2014
Event20th IEEE International On-Line Testing Symposium, IOLTS 2014 - Catalunya, Spain
Duration: 7 Jul 20149 Jul 2014

Conference

Conference20th IEEE International On-Line Testing Symposium, IOLTS 2014
CountrySpain
CityCatalunya
Period7/07/149/07/14

Fingerprint Dive into the research topics of 'A placement strategy for reducing the effects of multiple faults in digital circuits'. Together they form a unique fingerprint.

Cite this