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This paper proposes a fault-aware placement strategy for digital circuits. Placement algorithms usually have a goal of reducing the overall chip area and routing wirelength while the solution proposed in this paper focuses on reducing the effects of multiple faults caused by transients. The target circuits are properly analysed in order to identify scenarios that promote reductions in the overall error rate. The occurrence of these scenarios is then maximised when the proposed placement strategy is executed. Results show that substantial error rate reductions can be achieved.
|Title of host publication
|Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014
|IEEE Computer Society
|Number of pages
|Published - 2014
|20th IEEE International On-Line Testing Symposium, IOLTS 2014 - Catalunya, Spain
Duration: 7 Jul 2014 → 9 Jul 2014
|20th IEEE International On-Line Testing Symposium, IOLTS 2014
|7/07/14 → 9/07/14
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- 1 Finished
Pradhan, D. K.
1/10/09 → 1/03/13