A RAM based architecture for the implementation of bit-serial digital filters

David Bull; G Wacey; J Hansen

Abstract

Bit-serial implementations of digital signal processing algorithms often find favour where reduced implementation area is an important design criterion since they facilitate an efficient trade-off between silicon area and data throughput. Area-wise the adoption of a bit-serial regime not only offers single wire communication paths, but also allows the use of one-bit arithmetic operators. This paper presents a methodology and architecture which will facilitate the adoption of standard RAM compiled cells for bit serial digital filtering. The paper presents the method and general architecture, and describes a design which has been realised using this technique based on the Xilinx 4000 series FPGA. Finally, complexity comparisons are made between the new and conventional approaches

Original language	English
Pages	6/1 - 6/8
Publication status	Published - Nov 1992

Bibliographical note

Name of Conference: 12th Saraga Colloquium on Digital and Analogue Filters and Filtering Systems
Venue of Conference: London, UK

Access to Document

http://hdl.handle.net/1983/1322

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Cite this

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title = "A RAM based architecture for the implementation of bit-serial digital filters",

abstract = "Bit-serial implementations of digital signal processing algorithms often find favour where reduced implementation area is an important design criterion since they facilitate an efficient trade-off between silicon area and data throughput. Area-wise the adoption of a bit-serial regime not only offers single wire communication paths, but also allows the use of one-bit arithmetic operators. This paper presents a methodology and architecture which will facilitate the adoption of standard RAM compiled cells for bit serial digital filtering. The paper presents the method and general architecture, and describes a design which has been realised using this technique based on the Xilinx 4000 series FPGA. Finally, complexity comparisons are made between the new and conventional approaches",

author = "David Bull and G Wacey and J Hansen",

note = "Name of Conference: 12th Saraga Colloquium on Digital and Analogue Filters and Filtering Systems Venue of Conference: London, UK",

year = "1992",

month = nov,

language = "English",

pages = "6/1 -- 6/8",

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T1 - A RAM based architecture for the implementation of bit-serial digital filters

AU - Bull, David

AU - Wacey, G

AU - Hansen, J

N1 - Name of Conference: 12th Saraga Colloquium on Digital and Analogue Filters and Filtering Systems Venue of Conference: London, UK

PY - 1992/11

Y1 - 1992/11

N2 - Bit-serial implementations of digital signal processing algorithms often find favour where reduced implementation area is an important design criterion since they facilitate an efficient trade-off between silicon area and data throughput. Area-wise the adoption of a bit-serial regime not only offers single wire communication paths, but also allows the use of one-bit arithmetic operators. This paper presents a methodology and architecture which will facilitate the adoption of standard RAM compiled cells for bit serial digital filtering. The paper presents the method and general architecture, and describes a design which has been realised using this technique based on the Xilinx 4000 series FPGA. Finally, complexity comparisons are made between the new and conventional approaches

AB - Bit-serial implementations of digital signal processing algorithms often find favour where reduced implementation area is an important design criterion since they facilitate an efficient trade-off between silicon area and data throughput. Area-wise the adoption of a bit-serial regime not only offers single wire communication paths, but also allows the use of one-bit arithmetic operators. This paper presents a methodology and architecture which will facilitate the adoption of standard RAM compiled cells for bit serial digital filtering. The paper presents the method and general architecture, and describes a design which has been realised using this technique based on the Xilinx 4000 series FPGA. Finally, complexity comparisons are made between the new and conventional approaches

M3 - Conference Abstract

SP - 6/1 - 6/8