A Routing-Aware ILS Design Technique

Shibaji Banerjee*, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty

*Corresponding author for this work

Research output: Contribution to journalArticle (Academic Journal)peer-review

Abstract

The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flipflops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test set, to enhance fault coverage in broadcast mode. As a result, the number of serial test patterns also reduces.

Translated title of the contributionA Routing-Aware ILS Design Technique
Original languageEnglish
Article number-
Pages (from-to)2335-2338
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number12
DOIs
Publication statusPublished - Dec 2011

Keywords

  • DFT
  • scan testing
  • Illinois Scan Architecture (ILS)
  • CIRCUITS

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