A Routing-Aware ILS Design Technique

Shibaji Banerjee; Jimson Mathew; Dhiraj K. Pradhan; Bhargab B. Bhattacharya; Saraju P. Mohanty

doi:10.1109/TVLSI.2010.2078526

A Routing-Aware ILS Design Technique

Shibaji Banerjee^*
, Jimson Mathew
, Dhiraj K. Pradhan
, Bhargab B. Bhattacharya
, Saraju P. Mohanty

^*Corresponding author for this work

Microelectronics

Research output: Contribution to journal › Article (Academic Journal) › peer-review

Abstract

The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flipflops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test set, to enhance fault coverage in broadcast mode. As a result, the number of serial test patterns also reduces.

Translated title of the contribution	A Routing-Aware ILS Design Technique
Original language	English
Article number	-
Pages (from-to)	2335-2338
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	19
Issue number	12
DOIs	https://doi.org/10.1109/TVLSI.2010.2078526
Publication status	Published - Dec 2011

Keywords

DFT
scan testing
Illinois Scan Architecture (ILS)
CIRCUITS

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Cite this

@article{6768ed0b1c2d4f24a7a4b7c76bb441c8,

title = "A Routing-Aware ILS Design Technique",

abstract = "The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flipflops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test set, to enhance fault coverage in broadcast mode. As a result, the number of serial test patterns also reduces.",

keywords = "DFT, scan testing, Illinois Scan Architecture (ILS), CIRCUITS",

author = "Shibaji Banerjee and Jimson Mathew and Pradhan, \{Dhiraj K.\} and Bhattacharya, \{Bhargab B.\} and Mohanty, \{Saraju P.\}",

year = "2011",

month = dec,

doi = "10.1109/TVLSI.2010.2078526",

language = "English",

volume = "19",

pages = "2335--2338",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

number = "12",

}

TY - JOUR

T1 - A Routing-Aware ILS Design Technique

AU - Banerjee, Shibaji

AU - Mathew, Jimson

AU - Pradhan, Dhiraj K.

AU - Bhattacharya, Bhargab B.

AU - Mohanty, Saraju P.

PY - 2011/12

Y1 - 2011/12

N2 - The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flipflops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test set, to enhance fault coverage in broadcast mode. As a result, the number of serial test patterns also reduces.

AB - The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flipflops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test set, to enhance fault coverage in broadcast mode. As a result, the number of serial test patterns also reduces.

KW - DFT

KW - scan testing

KW - Illinois Scan Architecture (ILS)

KW - CIRCUITS

UR - http://www.cs.bris.ac.uk/Publications/pub_master.jsp?id=2001381

U2 - 10.1109/TVLSI.2010.2078526

DO - 10.1109/TVLSI.2010.2078526

M3 - Article (Academic Journal)

SN - 1063-8210

VL - 19

SP - 2335

EP - 2338

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IS - 12

M1 - -

ER -

A Routing-Aware ILS Design Technique

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PROCESS VARIATION AWARE SYNTHESIS OF NANO-CMOS CIRCUITS

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A Routing-Aware ILS Design Technique

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PROCESS VARIATION AWARE SYNTHESIS OF NANO-CMOS CIRCUITS

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