A Scalable Multi-Dimensional NoC Simulation Model for Diverse Spatio-Temporal Traffic Patterns

This paper describes a powerful simulation platform that enables accurate simulations of numerous network configurations under realistic traffic patterns to predict the performance and power needs of a 3-D integrated system early in the design flow. The simulation platform can model virtually any sized 2-D or 3-D network configuration, providing low-cost and fast tradeoff evaluations of various systems architectures. The network simulator uses scalable RTL-level models that can be used for accurate power and timing analyses. We demonstrate the capability of our simulation model by analyzing the performance of various network topologies under spatio-temporal traffic patterns to show how the network topology can be adjusted to meet the performance requirements of a design before it is manufactured. The simulation results can be used to optimize the placement of cores and communication buses early in the flow. By using the model, standard applications such as mobile application processor, femto-cell base-stations on-chip and wide-IO TSV memory stacking can be simulated.