Abstract
Within integrated circuit design, parasitic capacitance associated with the realisation of a resistor can limit circuit performance for certain applications, such as the analogue-to-digital converter. In this paper, a segmentation guarding layout technique is introduced that offers the circumvention of the parasitic capacitance of integrated resistors. The segmentation guarding technique is demonstrated on both diffusion and polysilicon integrated resistors.
Original language | English |
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Pages (from-to) | 1-7 |
Number of pages | 7 |
Journal | Analog Integrated Circuits and Signal Processing |
Early online date | 22 Apr 2017 |
DOIs | |
Publication status | E-pub ahead of print - 22 Apr 2017 |
Keywords
- CMOS
- Integrated resistor
- Parasitic capacitance
- Segmented layout guarding