A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors

Zhijun Zhou; Paul Warr

doi:10.1007/s10470-017-0982-7

A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors

Zhijun Zhou^*, Paul Warr

^*Corresponding author for this work

Research output: Contribution to journal › Article (Academic Journal) › peer-review

2 Citations (Scopus)

495 Downloads (Pure)

Abstract

Within integrated circuit design, parasitic capacitance associated with the realisation of a resistor can limit circuit performance for certain applications, such as the analogue-to-digital converter. In this paper, a segmentation guarding layout technique is introduced that offers the circumvention of the parasitic capacitance of integrated resistors. The segmentation guarding technique is demonstrated on both diffusion and polysilicon integrated resistors.

Original language	English
Pages (from-to)	1-7
Number of pages	7
Journal	Analog Integrated Circuits and Signal Processing
Early online date	22 Apr 2017
DOIs	https://doi.org/10.1007/s10470-017-0982-7
Publication status	E-pub ahead of print - 22 Apr 2017

Keywords

CMOS
Integrated resistor
Parasitic capacitance
Segmented layout guarding

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10.1007/s10470-017-0982-7

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title = "A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors",

abstract = "Within integrated circuit design, parasitic capacitance associated with the realisation of a resistor can limit circuit performance for certain applications, such as the analogue-to-digital converter. In this paper, a segmentation guarding layout technique is introduced that offers the circumvention of the parasitic capacitance of integrated resistors. The segmentation guarding technique is demonstrated on both diffusion and polysilicon integrated resistors.",

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T1 - A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors

AU - Zhou, Zhijun

AU - Warr, Paul

PY - 2017/4/22

Y1 - 2017/4/22

N2 - Within integrated circuit design, parasitic capacitance associated with the realisation of a resistor can limit circuit performance for certain applications, such as the analogue-to-digital converter. In this paper, a segmentation guarding layout technique is introduced that offers the circumvention of the parasitic capacitance of integrated resistors. The segmentation guarding technique is demonstrated on both diffusion and polysilicon integrated resistors.

AB - Within integrated circuit design, parasitic capacitance associated with the realisation of a resistor can limit circuit performance for certain applications, such as the analogue-to-digital converter. In this paper, a segmentation guarding layout technique is introduced that offers the circumvention of the parasitic capacitance of integrated resistors. The segmentation guarding technique is demonstrated on both diffusion and polysilicon integrated resistors.

KW - CMOS

KW - Integrated resistor

KW - Parasitic capacitance

KW - Segmented layout guarding

U2 - 10.1007/s10470-017-0982-7

DO - 10.1007/s10470-017-0982-7

M3 - Article (Academic Journal)

AN - SCOPUS:85018828059

SN - 0925-1030

SP - 1

EP - 7

JO - Analog Integrated Circuits and Signal Processing

JF - Analog Integrated Circuits and Signal Processing

ER -

A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors

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