A single-bit and double-adjacent error correcting parallel decoder for multiple-bit error correcting BCH codes

Kazuteru Namba, Salvatore Pontarelli, Marco Ottavi, Fabrizio Lombardi

Research output: Contribution to journalArticle (Academic Journal)peer-review

11 Citations (Scopus)

Abstract

This paper presents a novel high-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than double-adjacent errors. Its operation is based on extending an existing parallel BCH decoder that can only correct single-bit errors and serially corrects double-adjacent errors at low speed. The proposed decoder is constructed by a novel design and is suitable for nanoscale memory systems, in which multiple-bit errors occur at a probability comparable to single-bit errors and double-adjacent errors occur at a higher probability (nearly two orders of magnitude) than other multiple-bit errors. Extensive simulation results are reported. Compared with the existing scheme, the area and delay time of the proposed decoder are on average 11% and 6% higher, but its power consumption is reduced by 9% on average. This paper also shows that the area, delay, and power overheads incurred by the proposed scheme are significantly lower than traditional fully parallelized BCH decoders capable of correcting any double-bit errors in parallel.

Original languageEnglish
Article number6757028
Pages (from-to)664-671
Number of pages8
JournalIEEE Transactions on Device and Materials Reliability
Volume14
Issue number2
DOIs
Publication statusPublished - 1 Jan 2014

Keywords

  • BCH codes
  • double-adjacent error correction (DAEC)
  • Error correcting code (ECC)
  • parallel decoder

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