A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime

Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen

Research output: Contribution to journalArticle (Academic Journal)peer-review

Abstract

On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.
Original languageUndefined/Unknown
Pages (from-to)3 - 17
JournalIntegration, the VLSI Journal archive
Volume38
Issue number1
DOIs
Publication statusPublished - 2004

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