A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime

Dinesh Pamunuwa; Johnny Öberg; Li-Rong Zheng; Mikael Millberg; Axel Jantsch; Hannu Tenhunen

doi:10.1016/j.vlsi.2004.03.005

A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime

Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen

Research output: Contribution to journal › Article (Academic Journal) › peer-review

13 Citations (Scopus)

Abstract

On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

Original language	Undefined/Unknown
Pages (from-to)	3 - 17
Journal	Integration, the VLSI Journal archive
Volume	38
Issue number	1
DOIs	https://doi.org/10.1016/j.vlsi.2004.03.005
Publication status	Published - 2004

Research Groups and Themes

Photonics and Quantum

Access to Document

10.1016/j.vlsi.2004.03.005

http://www.sciencedirect.com/science/article/pii/S0167926004000203

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Cite this

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title = "A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime",

abstract = "On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.",

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AU - Pamunuwa, Dinesh

AU - Öberg, Johnny

AU - Zheng, Li-Rong

AU - Millberg, Mikael

AU - Jantsch, Axel

AU - Tenhunen, Hannu

PY - 2004

Y1 - 2004

N2 - On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

AB - On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

U2 - 10.1016/j.vlsi.2004.03.005

DO - 10.1016/j.vlsi.2004.03.005

M3 - Article (Academic Journal)

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