A system-on-chip vector multiprocessor for transmission line modelling acceleration

VA Chouliaras; JA Flint; Li Yibin; JL Nunez-Yanez

doi:10.1109/SIPS.2005.1579931

A system-on-chip vector multiprocessor for transmission line modelling acceleration

VA Chouliaras, JA Flint, Li Yibin, JL Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

2 Citations (Scopus)

Translated title of the contribution	A system-on-chip vector multiprocessor for transmission line modelling acceleration
Original language	English
Title of host publication	IEEE Workshop on Signal Processing Systems-Design and Implementation (IEEE Cat. No.05TH8830C), Greece
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	568 - 572
Number of pages	5
Volume	1
ISBN (Print)	0780393333
DOIs	https://doi.org/10.1109/SIPS.2005.1579931
Publication status	Published - 2 Nov 2005

Bibliographical note

Conference Proceedings/Title of Journal: IEEE Workshop on Signal Processing Systems-Design and Implementation (IEEE Cat. No.05TH8830C)
Conference Organiser: IEEE

Access to Document

10.1109/SIPS.2005.1579931

http://ieeexplore.ieee.org/iel5/10549/33371/01579931.pdf?tp=&arnumber=1579931&isnumber=33371

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Chouliaras, VA., Flint, JA., Yibin, L., & Nunez-Yanez, JL. (2005). A system-on-chip vector multiprocessor for transmission line modelling acceleration. In IEEE Workshop on Signal Processing Systems-Design and Implementation (IEEE Cat. No.05TH8830C), Greece (Vol. 1, pp. 568 - 572). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/SIPS.2005.1579931

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Chouliaras, VA, Flint, JA, Yibin, L & Nunez-Yanez, JL 2005, A system-on-chip vector multiprocessor for transmission line modelling acceleration. in IEEE Workshop on Signal Processing Systems-Design and Implementation (IEEE Cat. No.05TH8830C), Greece. vol. 1, Institute of Electrical and Electronics Engineers (IEEE), pp. 568 - 572. https://doi.org/10.1109/SIPS.2005.1579931

A system-on-chip vector multiprocessor for transmission line modelling acceleration. / Chouliaras, VA; Flint, JA; Yibin, Li et al.
IEEE Workshop on Signal Processing Systems-Design and Implementation (IEEE Cat. No.05TH8830C), Greece. Vol. 1 Institute of Electrical and Electronics Engineers (IEEE), 2005. p. 568 - 572.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

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AU - Chouliaras, VA

AU - Flint, JA

AU - Yibin, Li

AU - Nunez-Yanez, JL

N1 - Conference Proceedings/Title of Journal: IEEE Workshop on Signal Processing Systems-Design and Implementation (IEEE Cat. No.05TH8830C) Conference Organiser: IEEE

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M3 - Conference Contribution (Conference Proceeding)

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VL - 1

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EP - 572

BT - IEEE Workshop on Signal Processing Systems-Design and Implementation (IEEE Cat. No.05TH8830C), Greece

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -