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This paper proposes a systematic approach to help designers to optimise a given streaming application for FPGAs using High-Level Synthesis (HLS). The proposed technique specifically addresses the two main issues in a streaming application that are determining the exact amount of loop unrolling in the HLS code to increase the throughput and finding the optimum buffers' size to prevent deadlocks. To evaluate the proposed techniques two applications from the machine learning optimisation area are studied in the paper. These applications are Hessian-vector product and Conjugate Gradient (CG). The experimental results show up to 38× speed-up in throughput compared to the original streaming implementations provided by knowledgeable engineers using the dataflow, loop pipelining and FIFO channel related pragmas provided by the HLS tool. In addition, these applications show up to 2.98 GB/sec usage of memory bandwidth which is 93.1% of the total memory bandwidth available on the system. The source codes of the designs are available at https://github.com/Hosseinabady/csdfg-hls.
|Title of host publication||2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||4|
|Publication status||Published - 5 Oct 2017|
|Event||27th International Conference on Field Programmable Logic and Applications, FPL 2017 - Gent, Belgium|
Duration: 4 Sept 2017 → 6 Sept 2017
|Conference||27th International Conference on Field Programmable Logic and Applications, FPL 2017|
|Period||4/09/17 → 6/09/17|
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- 2 Finished
Nunez-Yanez, J. L.
5/01/16 → 4/01/20
Nunez-Yanez, J. L.
1/11/13 → 30/04/17