A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis

Mohammad Hosseinabady; Jose Luis Nunez-Yanez

doi:10.23919/FPL.2017.8056758

A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis

Mohammad Hosseinabady, Jose Luis Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

3 Citations (Scopus)

348 Downloads (Pure)

Abstract

This paper proposes a systematic approach to help designers to optimise a given streaming application for FPGAs using High-Level Synthesis (HLS). The proposed technique specifically addresses the two main issues in a streaming application that are determining the exact amount of loop unrolling in the HLS code to increase the throughput and finding the optimum buffers' size to prevent deadlocks. To evaluate the proposed techniques two applications from the machine learning optimisation area are studied in the paper. These applications are Hessian-vector product and Conjugate Gradient (CG). The experimental results show up to 38× speed-up in throughput compared to the original streaming implementations provided by knowledgeable engineers using the dataflow, loop pipelining and FIFO channel related pragmas provided by the HLS tool. In addition, these applications show up to 2.98 GB/sec usage of memory bandwidth which is 93.1% of the total memory bandwidth available on the system. The source codes of the designs are available at https://github.com/Hosseinabady/csdfg-hls.

Original language	English
Title of host publication	2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Number of pages	4
ISBN (Electronic)	9789090304281
ISBN (Print)	9781538620403
DOIs	https://doi.org/10.23919/FPL.2017.8056758
Publication status	Published - 5 Oct 2017
Event	27th International Conference on Field Programmable Logic and Applications, FPL 2017 - Gent, Belgium Duration: 4 Sept 2017 → 6 Sept 2017

Publication series

Name
ISSN (Electronic)	1946-1488

Conference

Conference	27th International Conference on Field Programmable Logic and Applications, FPL 2017
Country/Territory	Belgium
City	Gent
Period	4/09/17 → 6/09/17

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10.23919/FPL.2017.8056758

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title = "A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis",

abstract = "This paper proposes a systematic approach to help designers to optimise a given streaming application for FPGAs using High-Level Synthesis (HLS). The proposed technique specifically addresses the two main issues in a streaming application that are determining the exact amount of loop unrolling in the HLS code to increase the throughput and finding the optimum buffers' size to prevent deadlocks. To evaluate the proposed techniques two applications from the machine learning optimisation area are studied in the paper. These applications are Hessian-vector product and Conjugate Gradient (CG). The experimental results show up to 38× speed-up in throughput compared to the original streaming implementations provided by knowledgeable engineers using the dataflow, loop pipelining and FIFO channel related pragmas provided by the HLS tool. In addition, these applications show up to 2.98 GB/sec usage of memory bandwidth which is 93.1% of the total memory bandwidth available on the system. The source codes of the designs are available at https://github.com/Hosseinabady/csdfg-hls.",

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Hosseinabady, M & Nunez-Yanez, JL 2017, A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017., 8056758, Institute of Electrical and Electronics Engineers (IEEE), 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Gent, Belgium, 4/09/17. https://doi.org/10.23919/FPL.2017.8056758

A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. / Hosseinabady, Mohammad; Nunez-Yanez, Jose Luis.
2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers (IEEE), 2017. 8056758.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

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A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis

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ENergy Efficient Adaptive Computing with multi-grain heterogeneous architectures (ENEAC)

Energy Proportional Computing With Heterogeneous and Reconfigurable Processors (ENPOWER)

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A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis

Abstract

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ENergy Efficient Adaptive Computing with multi-grain heterogeneous architectures (ENEAC)

Energy Proportional Computing With Heterogeneous and Reconfigurable Processors (ENPOWER)

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