Abstract
We developed parametric data-parallel and scalar instruction set extensions for accelerating the ITU-T G.723.1 and G.729.A speech coding standards. Using a novel hybrid methodology, we synthesized the custom hardware accelerators via encapsulating the C-based descriptions of the original scalar and SIMD instruction set extensions in a hybrid, SystemC- RTL hardware wrapper and introduced it into the scalar and vector extension datapaths of a next-generation configurable, extensible multi-threaded CPU. We discuss this methodology and present a VLSI implementation of a 128-bit wide configuration of the data-parallel and scalar coprocessor attached to a dual-threaded instance of this CPU.
Translated title of the contribution | Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators |
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Original language | English |
Title of host publication | International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA, 7-11 January |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 279 - 280 |
Number of pages | 2 |
ISBN (Print) | 0780394593 |
DOIs | |
Publication status | Published - 7 Jan 2006 |
Bibliographical note
Conference Proceedings/Title of Journal: IEEE International Conference on Consumer Electronics (ICCE 2006), Las Vegas, USAConference Organiser: IEEE