Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators

K Koutsomyti; V Chouliaras; SR Parr; JL Nunez-Yanez; S Datta

doi:10.1109/ICCE.2006.1598419

Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators

K Koutsomyti, V Chouliaras, SR Parr, JL Nunez-Yanez, S Datta

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Abstract

We developed parametric data-parallel and scalar instruction set extensions for accelerating the ITU-T G.723.1 and G.729.A speech coding standards. Using a novel hybrid methodology, we synthesized the custom hardware accelerators via encapsulating the C-based descriptions of the original scalar and SIMD instruction set extensions in a hybrid, SystemC- RTL hardware wrapper and introduced it into the scalar and vector extension datapaths of a next-generation configurable, extensible multi-threaded CPU. We discuss this methodology and present a VLSI implementation of a 128-bit wide configuration of the data-parallel and scalar coprocessor attached to a dual-threaded instance of this CPU.

Translated title of the contribution	Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators
Original language	English
Title of host publication	International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA, 7-11 January
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	279 - 280
Number of pages	2
ISBN (Print)	0780394593
DOIs	https://doi.org/10.1109/ICCE.2006.1598419
Publication status	Published - 7 Jan 2006

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Conference Proceedings/Title of Journal: IEEE International Conference on Consumer Electronics (ICCE 2006), Las Vegas, USA
Conference Organiser: IEEE

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10.1109/ICCE.2006.1598419

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Koutsomyti, K., Chouliaras, V., Parr, SR., Nunez-Yanez, JL., & Datta, S. (2006). Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators. In International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA, 7-11 January (pp. 279 - 280). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ICCE.2006.1598419

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title = "Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators",

abstract = "We developed parametric data-parallel and scalar instruction set extensions for accelerating the ITU-T G.723.1 and G.729.A speech coding standards. Using a novel hybrid methodology, we synthesized the custom hardware accelerators via encapsulating the C-based descriptions of the original scalar and SIMD instruction set extensions in a hybrid, SystemC- RTL hardware wrapper and introduced it into the scalar and vector extension datapaths of a next-generation configurable, extensible multi-threaded CPU. We discuss this methodology and present a VLSI implementation of a 128-bit wide configuration of the data-parallel and scalar coprocessor attached to a dual-threaded instance of this CPU.",

author = "K Koutsomyti and V Chouliaras and SR Parr and JL Nunez-Yanez and S Datta",

note = "Conference Proceedings/Title of Journal: IEEE International Conference on Consumer Electronics (ICCE 2006), Las Vegas, USA Conference Organiser: IEEE",

year = "2006",

month = jan,

day = "7",

doi = "10.1109/ICCE.2006.1598419",

language = "English",

isbn = "0780394593",

pages = "279 -- 280",

booktitle = "International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA, 7-11 January",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

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}

Koutsomyti, K, Chouliaras, V, Parr, SR, Nunez-Yanez, JL & Datta, S 2006, Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators. in International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA, 7-11 January. Institute of Electrical and Electronics Engineers (IEEE), pp. 279 - 280. https://doi.org/10.1109/ICCE.2006.1598419

Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators. / Koutsomyti, K; Chouliaras, V; Parr, SR et al.
International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA, 7-11 January. Institute of Electrical and Electronics Engineers (IEEE), 2006. p. 279 - 280.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators

AU - Koutsomyti, K

AU - Chouliaras, V

AU - Parr, SR

AU - Nunez-Yanez, JL

AU - Datta, S

N1 - Conference Proceedings/Title of Journal: IEEE International Conference on Consumer Electronics (ICCE 2006), Las Vegas, USA Conference Organiser: IEEE

PY - 2006/1/7

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N2 - We developed parametric data-parallel and scalar instruction set extensions for accelerating the ITU-T G.723.1 and G.729.A speech coding standards. Using a novel hybrid methodology, we synthesized the custom hardware accelerators via encapsulating the C-based descriptions of the original scalar and SIMD instruction set extensions in a hybrid, SystemC- RTL hardware wrapper and introduced it into the scalar and vector extension datapaths of a next-generation configurable, extensible multi-threaded CPU. We discuss this methodology and present a VLSI implementation of a 128-bit wide configuration of the data-parallel and scalar coprocessor attached to a dual-threaded instance of this CPU.

AB - We developed parametric data-parallel and scalar instruction set extensions for accelerating the ITU-T G.723.1 and G.729.A speech coding standards. Using a novel hybrid methodology, we synthesized the custom hardware accelerators via encapsulating the C-based descriptions of the original scalar and SIMD instruction set extensions in a hybrid, SystemC- RTL hardware wrapper and introduced it into the scalar and vector extension datapaths of a next-generation configurable, extensible multi-threaded CPU. We discuss this methodology and present a VLSI implementation of a 128-bit wide configuration of the data-parallel and scalar coprocessor attached to a dual-threaded instance of this CPU.

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DO - 10.1109/ICCE.2006.1598419

M3 - Conference Contribution (Conference Proceeding)

SN - 0780394593

SP - 279

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BT - International Conference on Consumer Electronics (ICCE '06), Las Vegas, USA, 7-11 January

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

Accelerating speech coding standards through SystemC- synthesized SIMD and scalar accelerators

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