Accurate A Priori Signal Integrity Estimation Using a Multilevel Dynamic Interconnect Model for Deep Submicron VLSI Design

Li-Rong Zheng, Dinesh B Pamunuwa, Hannu Tenhunen

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

6 Citations (Scopus)

Abstract

A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design.
Original languageUndefined/Unknown
Title of host publicationProc. European Solid-State Circuits Conference
Publication statusPublished - 1 Sep 2000

Keywords

  • Circuit noise
  • Crosstalk
  • Electrical capacitance tomography
  • Integrated circuit interconnections
  • Routing
  • Signal analysis
  • Signal design
  • Timing
  • Very large scale integration
  • Wiring

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