Accurate A Priori Signal Integrity Estimation Using a Multilevel Dynamic Interconnect Model for Deep Submicron VLSI Design

Li-Rong Zheng; Dinesh B Pamunuwa; Hannu Tenhunen

Accurate A Priori Signal Integrity Estimation Using a Multilevel Dynamic Interconnect Model for Deep Submicron VLSI Design

Li-Rong Zheng, Dinesh B Pamunuwa, Hannu Tenhunen

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

6 Citations (Scopus)

Abstract

A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design.

Original language	Undefined/Unknown
Title of host publication	Proc. European Solid-State Circuits Conference
Publication status	Published - 1 Sep 2000

Keywords

Circuit noise
Crosstalk
Electrical capacitance tomography
Integrated circuit interconnections
Routing
Signal analysis
Signal design
Timing
Very large scale integration
Wiring

Cite this

@inproceedings{5f6bfccd94974ea39826d9e7b7dc0c3e,

title = "Accurate A Priori Signal Integrity Estimation Using a Multilevel Dynamic Interconnect Model for Deep Submicron VLSI Design",

abstract = "A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design.",

keywords = "Circuit noise, Crosstalk, Electrical capacitance tomography, Integrated circuit interconnections, Routing, Signal analysis, Signal design, Timing, Very large scale integration, Wiring",

author = "Li-Rong Zheng and Pamunuwa, {Dinesh B} and Hannu Tenhunen",

year = "2000",

month = sep,

day = "1",

language = "Undefined/Unknown",

booktitle = "Proc. European Solid-State Circuits Conference",

}

TY - GEN

T1 - Accurate A Priori Signal Integrity Estimation Using a Multilevel Dynamic Interconnect Model for Deep Submicron VLSI Design

AU - Zheng, Li-Rong

AU - Pamunuwa, Dinesh B

AU - Tenhunen, Hannu

PY - 2000/9/1

Y1 - 2000/9/1

N2 - A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design.

AB - A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design.

KW - Circuit noise

KW - Crosstalk

KW - Electrical capacitance tomography

KW - Integrated circuit interconnections

KW - Routing

KW - Signal analysis

KW - Signal design

KW - Timing

KW - Very large scale integration

KW - Wiring

M3 - Conference Contribution (Conference Proceeding)

BT - Proc. European Solid-State Circuits Conference

ER -