Achieving maximum performance: a method for the verification of interlocked pipeline control logic

KI Eder, G Barrett

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

Getting the interlock logic which controls pipeline flow correct is an important prerequisite for maximising pipeline performance. Unnecessary pipeline stalls can only be eliminated when they can be distinguished from those stalls which are necessary to preserve functional correctness. We propose a method for deriving a maximum pipeline performance specification from a complete functional specification of the pipeline control logic. The performance specification can be used to generate simulation testbench assertions. On the other hand, the specification can serve as a basis for formal property checking. The most promising aspect of our work is, however, the potential to synthesize the actual control logic from its formal description.
Translated title of the contributionAchieving maximum performance: a method for the verification of interlocked pipeline control logic
Original languageEnglish
Title of host publication39th Design Automation Conference, New Orleans, 10-14 June
PublisherAssociation for Computing Machinery (ACM)
Pages135 - 140
Number of pages6
VolumeSession 9.3
ISBN (Print)1581134614
DOIs
Publication statusPublished - Jun 2002

Bibliographical note

Other: http://www.cs.bris.ac.uk/Publications/pub_info.jsp?id=1000626

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