Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems

JL Nunez-Yanez, D Edwards, AM Coppola

Research output: Contribution to journalArticle (Academic Journal)peer-review

21 Citations (Scopus)
223 Downloads (Pure)

Abstract

An investigation into an effective and low-complexity adaptive routing strategy based on stochastic principles for an asynchronous network-on-chip platform that includes dynamically reconfigurable computing nodes is presented. The approach is compared with classic deterministic routing and it is shown to have good properties in terms of throughput and excellent fault-tolerance capabilities. The challenge of how to deliver reliability is one of the problems that multiprocessor system architects and manufactures will face as feature sizes and voltage supplies shrink and deep-submicron effects reduce the ability to carry out deterministic computing. It is likely that a new type of deep-submicron complex multicore systems will emerge which will be required to deliver high performance within strict energy and area budgets and operate over unreliable silicon. Within this context, the paper studies an on-chip communication infrastructure suitable for these systems.
Translated title of the contributionAdaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems
Original languageEnglish
Pages (from-to)184 - 198
Number of pages15
JournalIET Computers and Digital Techniques
Volume2
Issue number3
DOIs
Publication statusPublished - May 2008

Bibliographical note

Publisher: IET

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