An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate

Roshan Weerasekera, Guruprasad Katti, Rahul Dutta, Songbai Zhang, Ka Fai Chang, Jun Zhou, Surya Bhattacharya

Research output: Contribution to journal › Article (Academic Journal) › peer-review

11 Citations (Scopus)

Original language	Undefined/Unknown
Pages (from-to)	1182-1188
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	63
Issue number	3
DOIs	https://doi.org/10.1109/TED.2016.2522501
Publication status	Published - 2016

Research Groups and Themes

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title = "An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate",

author = "Roshan Weerasekera and Guruprasad Katti and Rahul Dutta and Songbai Zhang and Chang, \{Ka Fai\} and Jun Zhou and Surya Bhattacharya",

year = "2016",

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language = "Undefined/Unknown",

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journal = "IEEE Transactions on Electron Devices",

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T1 - An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate

AU - Weerasekera, Roshan

AU - Katti, Guruprasad

AU - Dutta, Rahul

AU - Zhang, Songbai

AU - Chang, Ka Fai

AU - Zhou, Jun

AU - Bhattacharya, Surya

PY - 2016

Y1 - 2016

U2 - 10.1109/TED.2016.2522501

DO - 10.1109/TED.2016.2522501

M3 - Article (Academic Journal)

SN - 0018-9383

VL - 63

SP - 1182

EP - 1188

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 3

ER -