An area-efficient, pulse-based interconnect

SJ Hollis; SW Moore

doi:10.1109/ISCAS.2006.1693120

An area-efficient, pulse-based interconnect

SJ Hollis, SW Moore

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

3 Citations (Scopus)

Abstract

We present a new style of long-distance, on-chip interconnect based loosely on the asynchronous GasP architecture, with a number of advantages over conventional interconnect. Most signi cant are a low wire count, a low area requirement, the absence of a global clock and simple composition with existing designs. We give some sample throughput and latency gures from simulation on a 0.18 m technology, and show that it is viable for use with modern interconnect requirements, is of low complexity, and has a lower area requirement than parallel interconnect over distances as short as 1mm.

Translated title of the contribution	An area-efficient, pulse-based interconnect
Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems, ISCAS 2006, Island of Kos, Greece, 21-24 May
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	21 - 24
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2006.1693120
Publication status	Published - May 2006

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Other page information: -
Conference Proceedings/Title of Journal: IEEE International Symposium on Circuits and Systems (ISCAS)
Other identifier: 2000798

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abstract = "We present a new style of long-distance, on-chip interconnect based loosely on the asynchronous GasP architecture, with a number of advantages over conventional interconnect. Most signi cant are a low wire count, a low area requirement, the absence of a global clock and simple composition with existing designs. We give some sample throughput and latency gures from simulation on a 0.18 m technology, and show that it is viable for use with modern interconnect requirements, is of low complexity, and has a lower area requirement than parallel interconnect over distances as short as 1mm. ",

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N2 - We present a new style of long-distance, on-chip interconnect based loosely on the asynchronous GasP architecture, with a number of advantages over conventional interconnect. Most signi cant are a low wire count, a low area requirement, the absence of a global clock and simple composition with existing designs. We give some sample throughput and latency gures from simulation on a 0.18 m technology, and show that it is viable for use with modern interconnect requirements, is of low complexity, and has a lower area requirement than parallel interconnect over distances as short as 1mm.

AB - We present a new style of long-distance, on-chip interconnect based loosely on the asynchronous GasP architecture, with a number of advantages over conventional interconnect. Most signi cant are a low wire count, a low area requirement, the absence of a global clock and simple composition with existing designs. We give some sample throughput and latency gures from simulation on a 0.18 m technology, and show that it is viable for use with modern interconnect requirements, is of low complexity, and has a lower area requirement than parallel interconnect over distances as short as 1mm.

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DO - 10.1109/ISCAS.2006.1693120

M3 - Conference Contribution (Conference Proceeding)

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BT - IEEE International Symposium on Circuits and Systems, ISCAS 2006, Island of Kos, Greece, 21-24 May

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

An area-efficient, pulse-based interconnect

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