An area-efficient, pulse-based interconnect

SJ Hollis, SW Moore

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

2 Citations (Scopus)

Abstract

We present a new style of long-distance, on-chip interconnect based loosely on the asynchronous GasP architecture, with a number of advantages over conventional interconnect. Most signi cant are a low wire count, a low area requirement, the absence of a global clock and simple composition with existing designs. We give some sample throughput and latency gures from simulation on a 0.18 m technology, and show that it is viable for use with modern interconnect requirements, is of low complexity, and has a lower area requirement than parallel interconnect over distances as short as 1mm.
Translated title of the contributionAn area-efficient, pulse-based interconnect
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems, ISCAS 2006, Island of Kos, Greece, 21-24 May
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages21 - 24
Number of pages4
DOIs
Publication statusPublished - May 2006

Bibliographical note

Other page information: -
Conference Proceedings/Title of Journal: IEEE International Symposium on Circuits and Systems (ISCAS)
Other identifier: 2000798

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