We present a new style of long-distance, on-chip interconnect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the most prominent being security enhancements, a reduction in the number of wires required, no need for clock distribution or packetization, and ease of composition. We give some sample throughput and latency figures from simulation on a 0.18 m technology and show that it is viable for use with modern interconnect requirements, is of low complexity and has a lower area requirement than parallel interconnect over distances as short as 1mm.
|Translated title of the contribution||An Asynchronous Interconnect Architecture for Device Security Enhancement|
|Title of host publication||VLSID '06|
|Subtitle of host publication||Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design|
|Publisher||Association for Computing Machinery (ACM)|
|Number of pages||7|
|Publication status||Published - 3 Jan 2006|