An Asynchronous Interconnect Architecture for Device Security Enhancement

Simon Hollis, Simon W. Moore

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

Abstract

We present a new style of long-distance, on-chip interconnect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the most prominent being security enhancements, a reduction in the number of wires required, no need for clock distribution or packetization, and ease of composition. We give some sample throughput and latency figures from simulation on a 0.18 m technology and show that it is viable for use with modern interconnect requirements, is of low complexity and has a lower area requirement than parallel interconnect over distances as short as 1mm.
Translated title of the contributionAn Asynchronous Interconnect Architecture for Device Security Enhancement
Original languageEnglish
Title of host publicationVLSID '06
Subtitle of host publicationProceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
PublisherAssociation for Computing Machinery (ACM)
Pages209-215
Number of pages7
ISBN (Print)0769525024
DOIs
Publication statusPublished - 3 Jan 2006

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