An asynchronous interconnect architecture for device security enhancement

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

1 Citation (Scopus)

Translated title of the contribution	An asynchronous interconnect architecture for device security enhancement
Original language	English
Title of host publication	19th International Conference on VLSI Design, Hyderabad, India, 3-7 January 2005
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	209 - 215
Number of pages	7
DOIs	https://doi.org/10.1109/VLSID.2006.40
Publication status	Published - Jan 2006

Access to Document

@inproceedings{0c57900e11734fbea1a5d1de585b98bf,

title = "An asynchronous interconnect architecture for device security enhancement",

author = "SJ Hollis and SW Moore",

year = "2006",

month = jan,

doi = "10.1109/VLSID.2006.40",

language = "English",

pages = "209 -- 215",

booktitle = "19th International Conference on VLSI Design, Hyderabad, India, 3-7 January 2005",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

An asynchronous interconnect architecture for device security enhancement. / Hollis, SJ; Moore, SW.
19th International Conference on VLSI Design, Hyderabad, India, 3-7 January 2005. Institute of Electrical and Electronics Engineers (IEEE), 2006. p. 209 - 215.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - An asynchronous interconnect architecture for device security enhancement

AU - Hollis, SJ

AU - Moore, SW

PY - 2006/1

Y1 - 2006/1

U2 - 10.1109/VLSID.2006.40

DO - 10.1109/VLSID.2006.40

M3 - Conference Contribution (Conference Proceeding)

SP - 209

EP - 215

BT - 19th International Conference on VLSI Design, Hyderabad, India, 3-7 January 2005

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -