TY - JOUR
T1 - An efficient technique to protect serial shift registers against soft errors
AU - Reviriego, Pedro
AU - Ruano, Oscar
AU - Flanagan, Mark F.
AU - Pontarelli, Salvatore
AU - Maestro, Juan A.
PY - 2013/7/18
Y1 - 2013/7/18
N2 - This brief presents a technique to efficiently correct single soft errors in serial shift registers. The proposed scheme uses two copies of the shift register. To achieve error correction, data are convolutionally encoded at the input of one of the copies and are decoded at its output. This processing ensures that in that copy, any error affecting a single bit will corrupt its output for multiple cycles. On the other hand, a single-bit error in the original copy will corrupt its output only for one cycle. Therefore, the error patterns can be used to identify the copy that has suffered the error and, consequently, to correct the error. The proposed technique has been implemented in a Hardware Description Language and implemented in a 45-nm library. A fault injection tool has been used to evaluate the effectiveness of the proposed scheme, showing that it can correct all single soft errors. The cost of the proposed approach in terms of circuit area has been compared with a traditional triple-modular redundancy implementation. The results show significant cost reductions, which approach a factor of 33% for large shift registers.
AB - This brief presents a technique to efficiently correct single soft errors in serial shift registers. The proposed scheme uses two copies of the shift register. To achieve error correction, data are convolutionally encoded at the input of one of the copies and are decoded at its output. This processing ensures that in that copy, any error affecting a single bit will corrupt its output for multiple cycles. On the other hand, a single-bit error in the original copy will corrupt its output only for one cycle. Therefore, the error patterns can be used to identify the copy that has suffered the error and, consequently, to correct the error. The proposed technique has been implemented in a Hardware Description Language and implemented in a 45-nm library. A fault injection tool has been used to evaluate the effectiveness of the proposed scheme, showing that it can correct all single soft errors. The cost of the proposed approach in terms of circuit area has been compared with a traditional triple-modular redundancy implementation. The results show significant cost reductions, which approach a factor of 33% for large shift registers.
KW - Delay lines
KW - modular redundancy
KW - shift registers
KW - soft errors
UR - http://www.scopus.com/inward/record.url?scp=84882816626&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2013.2268346
DO - 10.1109/TCSII.2013.2268346
M3 - Article (Academic Journal)
AN - SCOPUS:84882816626
VL - 60
SP - 512
EP - 516
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
SN - 1549-7747
IS - 8
M1 - 6553611
ER -