An efficient technique to select logic nodes for single event transient pulse-width reduction

Nihaar N Mahatme, Indranil Chatterjee, Akash Patki, Daniel B Limbrick, Bharat L Bhuva, Ronald D Schrimpf, William Robinson

Research output: Contribution to journalArticle (Academic Journal)

6 Citations (Scopus)
Original languageEnglish
Pages (from-to)114-117
Number of pages4
JournalMicroelectronics Reliability
Volume53
Issue number1
Publication statusPublished - 2013

Cite this

Mahatme, N. N., Chatterjee, I., Patki, A., Limbrick, D. B., Bhuva, B. L., Schrimpf, R. D., & Robinson, W. (2013). An efficient technique to select logic nodes for single event transient pulse-width reduction. Microelectronics Reliability, 53(1), 114-117.