Original language | English |
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Pages (from-to) | 114-117 |
Number of pages | 4 |
Journal | Microelectronics Reliability |
Volume | 53 |
Issue number | 1 |
Publication status | Published - 2013 |
An efficient technique to select logic nodes for single event transient pulse-width reduction
Nihaar N Mahatme, Indranil Chatterjee, Akash Patki, Daniel B Limbrick, Bharat L Bhuva, Ronald D Schrimpf, William Robinson
Research output: Contribution to journal › Article (Academic Journal) › peer-review
8
Citations
(Scopus)